Method and apparatus for digital frequency synthesis
First Claim
1. A wireless communication device comprising:
- a mixer including;
a first input for receiving a first signal that includes coded information;
a second input for receiving a locally generated signal for mixing with the first signal;
a digital frequency synthesizer including;
one or more delay lines including a plurality of output taps;
one or more clock signal sources coupled to the one or more delay lines;
one or more multiplexers including;
a plurality of signal inputs coupled to the plurality of output taps;
a plurality of address inputs; and
a common output coupled to the second input of the mixer; and
a controller including a plurality of control signal outputs coupled to the plurality of address inputs, for causing the one or more multiplexers to couple a plurality of output taps to the common output during a plurality of periods of a clock signal generated by at least one of the one or more clock signal sources.
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Accused Products
Abstract
A digital frequency synthesizer includes one or more reference clocks (104, 1316, 1502A, 1504A, 1506A) optionally coupled through one or more pulse width reducers (106) to one or more main delay lines (108, 702, 1502B, 1504B, 1506B) that include a plurality of output taps (108B-108I, 702B-702E). During at least certain periods of the reference clock (104) a plurality of the output taps are coupled to a common output (130, 1312, 1508), thereby producing an output signal that has a frequency that exceeds a frequency of the one or more reference clocks. The coupling is preferably accomplished by transmission gates (114, 128, 720-724, 1420-1434) that are switched by gating pulses that are received from decoders (148, 150, 1418) via gating signal delay lines (134-146, 704-718, 1404-1416).
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Citations
16 Claims
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1. A wireless communication device comprising:
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a mixer including;
a first input for receiving a first signal that includes coded information;
a second input for receiving a locally generated signal for mixing with the first signal;
a digital frequency synthesizer including;
one or more delay lines including a plurality of output taps;
one or more clock signal sources coupled to the one or more delay lines;
one or more multiplexers including;
a plurality of signal inputs coupled to the plurality of output taps;
a plurality of address inputs; and
a common output coupled to the second input of the mixer; and
a controller including a plurality of control signal outputs coupled to the plurality of address inputs, for causing the one or more multiplexers to couple a plurality of output taps to the common output during a plurality of periods of a clock signal generated by at least one of the one or more clock signal sources.
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2. A digital frequency synthesizer comprising:
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a clock signal source for outputting a clock signal that is characterized by a clock signal period;
a first delay line including;
a first delay line input coupled to the clock signal source; and
a plurality of first delay line output taps;
a plurality of transmission gates each of which include;
a first signal terminal coupled to one of the plurality of first delay line output taps;
a second signal terminal coupled to a common output; and
a gate control terminal;
a plurality of decoders each of which includes;
one or more decoder address inputs; and
a plurality of decoder outputs;
a plurality of gate signal delay lines each of which is characterized by one of a plurality of delay durations and includes;
an input that is coupled a decoder output of each of the plurality of decoders;
an output coupled to the gate control terminal of one of the plurality transmission gates, a controller including;
a set of control signal outputs coupled to the one or more decoder address inputs of the plurality of decoders. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A method of digitally synthesizing a signal, the method comprising the steps of:
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generating a clock signal that includes a plurality of successive clock signal periods;
reducing a pulse width of the clock signal;
coupling the clock signal to a delay line that includes;
an input end;
a plurality of taps including;
a zeroth tap that is located closest to the input end; and
a last tap that is furthest from the input end; and
during at least one clock signal period, selecting and coupling two or more of the plurality of taps to an output. - View Dependent Claims (13, 14, 15, 16)
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Specification