Ultra-miniature, high temperature, capacitive inductive pressure transducer

• US 6,891,711 B1
• Filed: 04/08/2004
• Issued: 05/10/2005
• Est. Priority Date: 04/08/2004
• Status: Expired due to Fees

• Current Assignee: Kulite Semiconductor Products Inc
• Original Assignee: Kulite Semiconductor Products Inc
• Inventors: Kurtz, Anthony D.
• Primary Examiner(s): Reichard, Dean A.
• Assistant Examiner(s): Ha, Nguyen T.
• Application Number:
  US10/820,357
• Time in Patent Office: 397 Days
• Field of Search: 361/277, 361/278, 361/281, 361/283.1, 361/283.3, 361/287, 361/290, 361/291, 361/293, 361/303, 361/305, 361/280, 361/286, 361/299.1
• US Class Current: 361/277
• CPC Class Codes: G01L 9/0073 using a semiconductive diaphragm
• CPC Class Codes: H01G 5/16 using variation of distance between electrodes

Abstract

An ultra miniature high temperature capacitive inductive pressure transducer is fabricated by MEMS techniques. The transducer consists of two separated pieces of silicon which form the plates of the capacitor, one of which plate is micromachined in such a way to allow a controlled deflection with pressure. The gap between the two capacitive plates is determined by an extending rim on one of the two plates. The two pieces of silicon are subsequently fusion bonded, leading a very small gap between the two plates. An inductor is formed on the top surface of one of the pieces of silicon by sputtering metal in a spiral like fashion on the back side of the non-micromachined plate.

Claims

1. A capacitor apparatus comprising:

a first semiconductor wafer having a top surface coated with a dielectric material and having disposed on said dielectric material a highly doped semiconductor first plate region surrounded by a highly doped first peripheral rim,

a second wafer having a dielectrically isolating top surface and having disposed on said top surface a second highly doped semiconductor plate region surrounded by a highly doped second peripheral rim, with said rim of said second wafer isolated from said second plate by a peripheral moat providing electrical isolation between said second plate and said second rim,

said first and second wafers bonded together at said rims to form a capacitor having said first and second plates spaced apart by a distance determined in part by the height of one of said rims.

2. The capacitor apparatus according to claim 1 wherein said first wafer has a recessed area on a bottom surface, said recessed area positioned with respect to said first plate to allow said first plate to deflect upon application of a force to said recessed area, whereby the value of capacitance changes with respect to said deflection and therefore, according to the magnitude of said force.

3. The capacitor apparatus according to claim 2 further comprising,

a spiral conductor disposed on the bottom surface of said second wafer, said inductor having first and second terminals located for connection to said first and second capacitor contacts to form a resonant circuit providing a frequency output proportional to said applied force.

4. The capacitor apparatus according to claim 3 wherein said inductor is a metal spiral deposited on said second wafer by RF sputtering or other deposition means.

5. The capacitor apparatus according to claim 3 further including means for hermetically sealing said resonant circuit in a housing.

6. The capacitor apparatus according to claim 1 further comprising a first aperture located on said second wafer and directed from a top to bottom surface to communicate with said bonded rims, said aperture filled with a conductive material to form a first contact for said capacitor,

a second aperture located on said second wafer and directed from said top to said bottom surface to contact said second plate, said second aperture filled with a conductive material to form a second contact for said capacitor.

7. The capacitor apparatus according to claim 1 wherein said first and second wafers are bonded together by a fusion bond.

8. The capacitor apparatus according to claim 1 wherein said first wafer is an N-type silicon wafer having a coating of silicon dioxide.

9. The capacitor apparatus according to claim 8 wherein said highly doped regions are P+diffused regions.

10. The capacitor apparatus according to claim 1 wherein said second wafer is a Pyrex glass wafer.

11. The capacitor apparatus according to claim 1, wherein said second wafer is an N-type silicon wafer with said dielectrically isolating top surface being a layer of silicon dioxide.

12. The capacitor apparatus according to claim 1 wherein said first and second plate regions are relatively congruent.

13. The capacitor apparatus according to claim 1 wherein said rim of said second wafer is higher than said second plate area.

14. The capacitor apparatus according to claim 1 wherein said rim of said second wafer is the same height as said second plate area.

15. The capacitor apparatus according to claim 1 wherein said first plate region is generally rectangular in shape and having an extending tab on one side.

16. The capacitor apparatus according to claim 15 wherein said second plate region is generally rectangular in shape and having an extending tab on one side and is relatively congruent to said first plate region when said extending tabs facing each other.

17. The capacitor apparatus according to claim 16 wherein said extending tab of said second plate region is a contact tab to provide a contact area for said second plate region.

18. The capacitor apparatus according to claim 1 wherein the height of said first rim determines the spacing between said first and second plate regions and, therefore the magnitude of said capacitor.

19. The capacitor apparatus according to claim 1 wherein the height of said second rim determines the spacing between said first and second plate regions and, therefore, the magnitude of said capacitor.

20. The capacitor apparatus according to claim 1 wherein said highly doped semiconductor first plate and said first rim are disposed on said dielectric material by a fusion bond.