Ultra-miniature, high temperature, capacitive inductive pressure transducer
First Claim
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1. A capacitor apparatus comprising:
- a first semiconductor wafer having a top surface coated with a dielectric material and having disposed on said dielectric material a highly doped semiconductor first plate region surrounded by a highly doped first peripheral rim, a second wafer having a dielectrically isolating top surface and having disposed on said top surface a second highly doped semiconductor plate region surrounded by a highly doped second peripheral rim, with said rim of said second wafer isolated from said second plate by a peripheral moat providing electrical isolation between said second plate and said second rim, said first and second wafers bonded together at said rims to form a capacitor having said first and second plates spaced apart by a distance determined in part by the height of one of said rims.
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Abstract
An ultra miniature high temperature capacitive inductive pressure transducer is fabricated by MEMS techniques. The transducer consists of two separated pieces of silicon which form the plates of the capacitor, one of which plate is micromachined in such a way to allow a controlled deflection with pressure. The gap between the two capacitive plates is determined by an extending rim on one of the two plates. The two pieces of silicon are subsequently fusion bonded, leading a very small gap between the two plates. An inductor is formed on the top surface of one of the pieces of silicon by sputtering metal in a spiral like fashion on the back side of the non-micromachined plate.
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Citations
20 Claims
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1. A capacitor apparatus comprising:
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a first semiconductor wafer having a top surface coated with a dielectric material and having disposed on said dielectric material a highly doped semiconductor first plate region surrounded by a highly doped first peripheral rim, a second wafer having a dielectrically isolating top surface and having disposed on said top surface a second highly doped semiconductor plate region surrounded by a highly doped second peripheral rim, with said rim of said second wafer isolated from said second plate by a peripheral moat providing electrical isolation between said second plate and said second rim, said first and second wafers bonded together at said rims to form a capacitor having said first and second plates spaced apart by a distance determined in part by the height of one of said rims. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification