Multiple operating system control method
First Claim
1. A multiple operating system control apparatus for a multiple operating system having plural operating systems executed in a digital arithmetic processor and including a first operating system and a second operating system and a plurality of pieces of hardware, each piece of hardware assigned to a corresponding operating system, comprising:
- respective pieces of hardware having assigned interrupt numbers stored in a table so as to maintain the operating systems independent from each other;
the digital arithmetic processor programmed to alternately switch, under inter-operating system control software control, on the basis of said table, between and said first and second operating systems to alternately execute said first and second operating systems; and
an interrupt number or an input and output address used by said second operating system for said first operating system when starting said first operating system being reserved.
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Accused Products
Abstract
An inter-OS control software for switching OS'"'"'s in operation executed on a single CPU is installed, and plural OS'"'"'s are made alternately executed. A control program is executed exclusively on one OS, which controls the controlled apparatus. A supervisory control program and a development environment program are executed on another OS, and a memory space is divided so as to make no effect for the operation of the control program. A higher real-time performance and reliability can be established with a single CPU architecture.
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Citations
29 Claims
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1. A multiple operating system control apparatus for a multiple operating system having plural operating systems executed in a digital arithmetic processor and including a first operating system and a second operating system and a plurality of pieces of hardware, each piece of hardware assigned to a corresponding operating system, comprising:
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respective pieces of hardware having assigned interrupt numbers stored in a table so as to maintain the operating systems independent from each other;
the digital arithmetic processor programmed to alternately switch, under inter-operating system control software control, on the basis of said table, between and said first and second operating systems to alternately execute said first and second operating systems; and
an interrupt number or an input and output address used by said second operating system for said first operating system when starting said first operating system being reserved. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. An apparatus comprising:
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a. a digital arithmetic processor having at least a first operating system and a second operating system operating therein, said processor having inter-operating system control software to switch therebetween;
b. a plurality of pieces of hardware, each piece of hardware assigned to a corresponding operating system, with respective pieces of hardware having assigned interrupt numbers stored in a table so as to maintain the operating systems independent from each other. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A multiple operating system comprising:
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a. a digital arithmetic processor having plural operating systems executed therein including a first operating system and a second operating system;
b. and a plurality of pieces of hardware, each piece of hardware assigned to a corresponding operating system, said respective pieces of hardware having assigned interrupt numbers;
c. a table storing said assigned interrupt numbers so as to maintain the operating systems independent from each other, the digital arithmetic processor programmed to alternately switch, under inter-operating system control software control, on the basis of said table, between and said first and second operating systems to alternately execute said first and second operating systems; and
d. an interrupt number or an input and output address used by said second operating system for said first operating system when starting said first operating system being reserved. - View Dependent Claims (21, 22, 23, 24, 25, 26, 27, 28, 29)
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Specification