Synchronous flash memory emulating the pin configuration of SDRAM

• US 6,892,270 B2
• Filed: 02/25/2004
• Issued: 05/10/2005
• Est. Priority Date: 07/28/2000
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Roohparvar, Frankie F.
• Primary Examiner(s): Peikari, B. James
• Application Number:
  US10/786,353
• Publication Number:
  US 20040165447A1
• Time in Patent Office: 440 Days
• Field of Search: 711/105, 711/104, 711/166, 711/101, 326/101, 365/189.01, 365/193, 365/226, 365/233, 712/224, 713/300, 713/400
• US Class Current: 711/105
• CPC Class Codes: G06F 13/1668 Details of memory controller
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 2207/105 Aspects related to pads, pins or terminals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 8/18 Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A computer system comprises a memory controller and a synchronous non-volatile memory device coupled to the memory controller via a main memory bus. The synchronous non-volatile memory device has external interconnects arranged in a manner that corresponds to interconnects of a synchronous dynamic random access memory device. The synchronous flash memory device, however, comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory. In one embodiment, the synchronous non-volatile memory device has a command interface comprising a write enable connection (WE#) to receive a write enable signal, a column address strobe connection (CAS#) to receive a column address strobe signal, a row address strobe connection (RAS#) to receive a row address strobe signal, and a chip select connection (CS#) to receive a chip select signal.

Claims

1. A synchronous flash memory device comprising:

an array of non-volatile memory cells; and

a plurality of external connections comprising,

a plurality of bi-directional data connections,

a plurality of memory address connections,

a clock input connection,

a write enable connection,

a column address strobe connection,

a row address strobe connection, and

wherein the plurality of external connections are arranged in a pattern compatible

with a synchronous dynamic random access memory (SDRAM).

2. The synchronous flash memory device of claim 1, wherein the plurality of external connections further comprises:

a clock enable connection,

a chip select connection,

a plurality of memory array bank address connections,

power supply connections,

a plurality of data mask connections, and

a reset connection.

3. The synchronous flash memory device of claim 1, wherein the plurality of external connections further comprises a Vccp power supply connection.

4. The synchronous flash memory device of claim 1, further comprising a package having a plurality of interconnect pins corresponding to the external connections.

5. The synchronous flash memory device of claim 1, further comprising a package having a plurality of conductive interconnect locations corresponding to the external connections.

6. The synchronous flash memory device of claim 1, wherein the synchronous flash memory device operates within read timing specification parameters for an SDRAM.

7. A synchronous flash memory device comprising:

an array of non-volatile memory cells; and

a package having a plurality of interconnect pins arranged in a manner that corresponds to interconnect pins of a synchronous dynamic random access memory device, wherein the plurality of interconnect pins of the synchronous flash memory device comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory.

8. The synchronous flash memory device of claim 7, wherein the plurality of interconnect pins comprises:

a plurality of bi-directional data connections,

a plurality of memory address connections,

a write enable connection,

a clock input connection,

a column address strobe connection,

a row address strobe connection, and

power supply connections.

9. The synchronous flash memory device of claim 8, wherein the plurality of interconnect pins further comprises:

a clock enable connection,

a chip select connection,

a plurality of memory array bank address connections,

a plurality of data mask connections,

a reset connection, and

a Vccp power supply connection.

10. A synchronous flash memory device comprising:

an array of non-volatile memory cells; and

a package having a plurality of solder bump connections arranged in a manner that corresponds to solder bump connections of a synchronous dynamic random access memory device, wherein the plurality of solder bump connections of the synchronous flash memory device comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) solder bump connections of the synchronous dynamic random access memory.

11. The synchronous flash memory device of claim 10, wherein the plurality of solder bump connections comprises:

a plurality of bi-directional data connections,

a plurality of memory address connections,

a write enable connection,

a clock input connection,

a column address strobe connection,

a row address strobe connection, and

power supply connections.

12. The synchronous flash memory device of claim 11, wherein the plurality of interconnect pins further comprises:

a clock enable connection,

a chip select connection,

a plurality of memory array bank address connections,

a plurality of data mask connections,

a reset connection, and

a Vccp power supply connection.

13. A synchronous flash memory device having an interface comprising:

a clock input connection (CLK) to receive a clock signal;

a write enable connection (WE#) to receive a write enable signal;

a column address strobe connection (CAS#) to receive a column address strobe signal;

a row address strobe connection (RAS#) to receive a row address strobe signal;

a chip select connection (CS#) to receive a chip select signal;

a reset connection (RP#) to receive a reset signal;

a Vccp power supply connection to receive an elevated power supply signal; and

a plurality of external connections, wherein the plurality of external connections are arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM).

14. The synchronous flash memory device of claim 13, wherein the interface further comprises:

a plurality of bi-directional data connections (DQ);

a plurality of memory address connections;

a clock enable connection (CKE);

a plurality of memory array bank address connections (BA#);

power supply connections (Vcc and Vss); and

a plurality of data mask connections (DQM).

15. The synchronous flash memory device of claim 14, further comprising a package having a plurality of interconnect pins corresponding to the command interface connections.

16. The synchronous flash memory device of claim 14, further comprising a package having a plurality of conductive interconnect locations corresponding to the command interface connections.

17. A computer system comprising:

a memory controller;

a main memory bus coupled to the memory controller, and

a synchronous non-volatile flash memory device coupled to the main memory bus,

wherein the synchronous non-volatile flash memory device has a plurality of external connections are arranged in a pattern compatible with a synchronous dynamic random access memory (SDRAM) and a command interface comprising;

a write enable connection (WE#) to receive a write enable signal;

a column address strobe connection (CAS#) to receive a column address strobe signal;

a row address strobe connection (RAS#) to receive a row address strobe signal; and

a chip select connection (CS#) to receive a chip select signal.

18. The computer system of claim 17, wherein the synchronous non-volatile flash memory device comprises a package having a plurality of interconnect pins arranged in a manner that corresponds to interconnect pins of a synchronous dynamic random access memory device, wherein the plurality of interconnect pins of the synchronous flash memory device comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) interconnect pins of the synchronous dynamic random access memory.

19. The computer system of claim 17, wherein the synchronous non-volatile flash memory device comprises a package having a plurality of solder bump connections arranged in a manner that corresponds to solder bump connections of a synchronous dynamic random access memory device, wherein the plurality of solder bump connections of the synchronous flash memory device comprises a reset connection, and a Vccp power supply connection correspond to first and second no-connect (NC) solder bump connections of the synchronous dynamic random access memory.

20. The computer system of claim 17, wherein the plurality of external connections comprise:

a plurality of bi-directional data connections;

a plurality of memory address connections;

a clock input connection;

a clock enable connection;

a plurality of memory array bank address connections;

power supply connections;

a plurality of data mask connections;

a reset connection; and

a Vccp power supply connection.