VLIW processor and method therefor

• US 6,892,293 B2
• Filed: 04/09/1998
• Issued: 05/10/2005
• Est. Priority Date: 11/05/1993
• Status: Expired due to Fees

• Current Assignee: Intergraph Hardware Technologies Company (Hexagon AB)
• Original Assignee: Intergraph Corporation (Hexagon AB)
• Inventors: Arya, Siamak, Sachs, Howard G.
• Primary Examiner(s): VU, VIET DUY
• Application Number:
  US09/057,861
• Publication Number:
  US 20030191923A1
• Time in Patent Office: 2,588 Days
• Field of Search: 712/23, 712/24, 712/206, 712/208, 712/213, 712/214, 712/215, 712/216, 712/233, 712/234
• US Class Current: 712/215
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/382 Pipelined decoding, e.g. using predecoding
• CPC Class Codes: G06F 9/3853 of compound instructions
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A computing system as described in which individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. The system includes storage for storing an arbitrary number of the instructions to be executed. The instructions to be executed are tagged with pipeline identification tags indicative of the pipeline to which they should be dispatched. The pipeline identification tags are supplied to a system which controls a crossbar switch, enabling the tags to be used to control the switch and supply the appropriate instructions simultaneously to the differing pipelines.

Claims

1. A method for operating a computing system comprises:

fetching a first 256 bit-wide frame of instructions from an instruction memory, the first frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of instructions from the first frame of instructions, wherein the groups of instructions comprise at least one group of instructions and comprise at most eight groups of individual instructions, wherein a group of instructions are issued separately from other groups of instructions within the first frame of instructions, wherein groups of instructions are issued from left-to-right from the first frame of instructions, and wherein instructions within a group of instructions are issued in parallel;

issuing instructions in a first group of instructions from the first frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the first frame of instructions;

fetching a second 256 bit-wide frame of instructions from the instruction memory, the second frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of instructions from the second frame of instructions, wherein the groups of instructions comprise at least one group of instructions and comprise at most eight groups of individual instructions, wherein a group of instructions are issued separately from other groups of instructions within the second frame of instructions, wherein groups of instructions are issued from left-to-right from the second frame of instructions, and wherein instructions within a group of instructions are issued in parallel; and

issuing instructions in a first group of instructions from the second frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the second frame of instructions;

wherein instructions from the first 256 bit-wide frame of instructions are issued before fetching the second 256 bit-wide frame of instructions from the instruction memory; and

wherein the grouping bits of the 32 bit-wide instructions from the first frame of instructions and the grouping bits of the 32 bit-wide instructions from the second frame of instructions are specifiable at compile time.

2. The method of claim 1 wherein the first 256 bit-wide frame of instructions comprises less then eight 32 bit-wide instructions.

3. The method of claim 1 further comprising:

issuing instructions in a second group of instructions from the first frame of instructions to functional units appropriate for the instructions in the second group of instructions in response to grouping bits of the instructions in the second group of instructions and in response to a mapping of the instructions in the second group of instructions to functional units, wherein the mapping is determined in response to a portion of instruction data in each instruction in the second group of instructions from the first frame of instructions.

4. The method of claim 3 wherein a functional unit appropriate for an instruction in the second group of instructions from the first frame of instruction comprises a floating point unit.

5. The method of claim 4 wherein the second group of instructions from the first frame of instructions includes a floating point instruction.

6. The method of claim 1 wherein the first 256 bit-wide frame of instructions comprises exactly eight 32 bit-wide instructions.

7. The method of claim 6 further comprising:

issuing instructions in a second group of instructions from the second frame of instructions to functional units appropriate for the instructions in the second group of instructions in response to grouping bits of the instructions in the second group of instructions and in response to a mapping of the instructions in the second group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the second group of instructions from the second frame of instructions.

8. The method of claim 1 wherein three groups of instructions are packed within the first 256 bit-wide frame of instructions thereby reducing instruction code size.

9. The method of claim 8 wherein issuing instructions in a first group of instructions from the first frame of instructions further comprises decoding the instructions in the first group of instructions before issuance to functional units appropriate for the instructions in the first group of instructions from the first frame of instructions.

10. The method of claim 1 wherein four groups of instructions are packed within the first 256 bit-wide frame of instructions thereby reducing a number of no-operations within the first 256 bit-wide frame of instructions.

11. The method of claim 10 wherein groups of instructions are not split across the first 256 bit-wide frame of instructions and the second 256 bit-wide frame of instructions.

12. The method of claim 10 wherein the grouping bits of the 32 bit-wide instructions from the first frame of instructions and the grouping bits of the 32 bit-wide instructions from the second frame of instructions are specified at compile time in response to data dependency checking of the instructions in the first frame of instructions and in response to data dependency checking of the instructions in the second frame of instructions.

13. The method of claim 1 wherein the instructions in the first instruction frame are stored in little-endian format.

14. The method of claim 13 wherein the functional units appropriate for the instructions in the first group of instructions in the first frame of instructions are selected from a group of eight functional units.

15. The method of claim 1

wherein the groups of instructions from the first frame of instructions comprise the first group of instructions, a second group of instructions, and a third group of instructions;

wherein instructions grouped as the second group of instructions are to be issued in parallel to appropriate functional units before instructions grouped as the third group of instructions are to be issued in parallel.

16. The method of claim 15

wherein the first group of instructions comprises two instructions to be issued in parallel;

wherein the second group of instructions comprises three instructions to be issued in parallel; and

wherein the third group of instructions comprises three instructions to be issued in parallel.

17. The method of claim 15

wherein the groups of instructions from the first frame of instructions also comprise a fourth group of instructions;

wherein instructions grouped as the third group of instructions are to be issued in parallel to appropriate functional units before instructions grouped as the fourth group of instructions are to be issued in parallel;

wherein the third group of instructions comprises two instructions to be issued in parallel; and

wherein the fourth group of instructions comprises two instructions to be issued in parallel.

18. The method of claim 1 wherein the first group of instructions from the first frame of instructions includes two add instructions that are issued in parallel to functional units appropriate for the two add instructions.

19. The method of claim 18 wherein the functional units include two arithmetic logic units.

20. The method of claim 18 wherein the first group of instructions from the first frame of instructions also includes a load instruction.

21. The method of claim 1 wherein an instruction in the first group of instructions from the first frame of instructions operates upon registers.

22. The method of claim 21 wherein an instructions from the first frame of instructions comprises a branch instruction.

23. A processor comprises:

a plurality of functional units;

an instruction memory configured to store a first 256-bit wide frame of instructions, the first frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of variable length groups of instructions from the first frame of instructions, wherein the variable length groups of instructions comprise at least one group of instructions and comprise at most eight groups of individual instructions, wherein a group of instructions are dispatched separately from other groups of instructions within the first frame of instructions, wherein groups of instructions are dispatched from left-to-right from the first frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel; and

an instruction dispatching unit coupled to the instruction memory and the plurality of functional units, the instruction dispatching unit configured to dispatch instructions in a first group of instructions from the first frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the first frame of instructions; and

wherein the grouping bits of the 32 bit-wide instructions from the first frame of instructions are determinable at compile time.

24. The processor of claim 23

wherein the instruction memory is also configured to store a second 256 bit-wide frame of instructions, the second frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of variable length groups of instructions from the second frame of instructions, wherein the variable length groups of instructions comprise at least one group of instructions and comprise at most eight groups of individual instructions, wherein a group of instructions are dispatched separately from other groups of instructions within the second frame of instructions, wherein groups of instructions are dispatched from left-to-right from the second frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel;

wherein the instruction dispatching unit is also configured to dispatch instructions in a first group of instructions from the second frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the second frame of instructions; and

wherein the first group of instructions from the first 256-bit wide frame of instructions are dispatched before the first group of instruction in the second 256 bit-wide frame of instructions.

25. The processor of claim 24 wherein the instruction dispatching unit is also configured to dispatch instructions in a second group of instructions from the first frame of instructions to functional units appropriate for the instructions in the second group of instructions in response to grouping bits of the instructions in the second group of instructions and in response to a mapping of the instructions in the second group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the second group of instructions from the first frame of instructions.

26. The processor of claim 25 wherein the first 256 bit-wide frame of instructions comprises less than eight 32 bit-wide instructions and a no operation.

27. The processor of claim 23 wherein the plurality of functional units comprises a functional unit configured to perform floating-point operations.

28. The processor of claim 27 wherein an instruction in the first frame of instructions comprises a floating point instruction.

29. The processor of claim 23 wherein the plurality of functional units also comprises a functional unit configured to perform a load operation and a store operation.

30. The processor of claim 29 wherein the plurality of functional units also comprises a functional unit configured to perform branch instructions.

31. The processor of claim 30 wherein the first 256 bit-wide frame of instructions comprises exactly eight 32 bit-wide instructions.

32. The processor of claim 23 wherein at least three groups of instructions are packed within the first 256 bit-wide frame of instructions thereby saving memory space.

33. The processor of claim 32 wherein the instruction dispatching unit is also configured to fetch the first frame of instructions and configured to decode the instructions in the first group of instructions before dispatch to functional units appropriate for the instructions in the first group of instructions from the first frame of instructions.

34. The processor of claim 23 wherein groups of instructions to be dispatched in parallel are not split across frames of instructions.

35. The processor of claim 34 wherein four groups of instructions are packed within the first 256 bit-wide frame of instructions thereby reducing memory bandwidth.

36. The processor of claim 34 wherein the grouping bits of the 32 bit-wide instructions from the first frame of instructions are determined at compile time in response to data dependency checking of the instructions in the first frame of instructions.

37. The processor of claim 23 wherein the functional units appropriate for the instructions in the first group of instructions in the first frame of instructions are selected from a group of eight functional units.

38. The processor of claim 37 wherein the instructions in the first instruction frame are stored in little-endian format.

39. The processor of claim 23

wherein the groups of instructions from the first frame of instructions comprise the first group of instructions, a second group of instructions, and a third group of instructions;

wherein the instruction dispatching unit is also configured to dispatch instructions in a second group of instructions from the first frame of instructions to functional units appropriate for the instructions in the second group of instructions in response to grouping bits of the instructions in the second group of instructions and in response to a mapping of the instructions in the second group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the second group of instructions from the first frame of instructions; and

wherein the instruction dispatching unit is also configured to dispatch instructions grouped as the first group of instructions in parallel to appropriate functional units before dispatching instructions grouped as the second group of instructions in parallel.

40. The processor of claim 39

wherein the first group of instructions comprises two instructions to be dispatched in parallel;

wherein the second group of instructions comprises three instructions to be dispatched in parallel; and

wherein the third group of instructions comprises three instructions to be dispatched in parallel.

41. The processor of claim 39

wherein the groups of instructions from the first frame of instructions also comprise a fourth group of instructions;

wherein the instruction dispatching unit is also configured to dispatch instructions in a third group of instructions from the first frame of instructions to functional units appropriate for the instructions in the third group of instructions in response to grouping bits of the instructions in the third group of instructions and in response to a mapping of the instructions in the third group of instructions to functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the third group of instructions from the first frame of instructions;

wherein the instruction dispatching unit is also configured to dispatch instructions grouped as the second group of instructions in parallel to appropriate functional units before dispatching instructions grouped as the third group of instructions in parallel;

wherein the third group of instructions comprises two instructions to be dispatched in parallel; and

wherein the fourth group of instructions comprises two instructions to be dispatched in parallel.

42. The processor of claim 23 wherein the plurality of functional units include functional units configured to perform arithmetic and logic operations.

43. The processor of claim 42 wherein an instruction of the first group of instructions from the first frame of instructions comprises a load instruction.

44. The processor of claim 42 wherein the instructions of the first group from the first frame of instructions comprises two addition instructions.

45. The processor of claim 42 wherein at least one instruction in the first group of instructions from the first frame of instructions operates upon registers.

46. The processor of claim 42 wherein an instruction from the first frame of instructions comprises a branch instruction.

64. The apparatus of claim 42

wherein the plurality of functional units includes at least two arithmetic logic units;

and

wherein the first group of instructions from the first frame of instructions comprises two addition instructions.

65. The apparatus of claim 64 wherein the first group of instructions from the first frame of instructions also comprise a load instruction.

66. The apparatus of claim 65 wherein the two addition instructions operate upon registers.

47. An apparatus comprises:

a memory configured to store a plurality of instruction data; and

a processor coupled to the memory comprising;

a memory controller configured to receive a first set of instruction data from the memory;

a plurality of functional units;

an instruction memory configured to store a first 256-bit wide frame of instructions in response to the first set of instruction data from the memory, the first frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of instructions of variable lengths from the first frame of instructions, wherein the groups of instructions comprise at least one group of instructions and comprise at most eight groups of instructions, wherein a number of instructions in the groups of instructions comprises at least one instruction and up to eight instructions, wherein a group of instructions are dispatched separately from other groups of instructions within the first frame of instructions, wherein groups of instructions are dispatched from left-to-right from the first frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel; and

an instruction dispatching unit coupled to the instruction memory and coupled to the plurality of functional units, the instruction dispatching unit configured to fetch the first frame of instructions from the instruction memory and configured to dispatch instructions in a first group of instructions from the first frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to appropriate functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the first frame of instructions;

wherein the grouping bits of the instructions in the first group of instructions from the first frame of instructions are determinable at compile time.

48. The apparatus of claim 47

wherein the memory controller is configured to receive a second set of instruction data from the memory;

wherein the instruction memory is also configured to store a second 256-bit wide frame of instructions in response to the second set of instruction data from the memory, the second frame of instructions comprising up to eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of instructions of variable lengths from the second frame of instructions, wherein the groups of instructions comprise at least one group of instructions and comprise at most eight groups of instructions, wherein a number of instructions in the groups of instructions comprises at least one instruction and up to eight instructions, wherein a group of instructions are dispatched separately from other groups of instructions within the second frame of instructions, wherein groups of instructions are dispatched from left-to-right from the first frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel; and

wherein the instruction dispatching unit is also configured to fetch the second frame of instructions from the instruction memory and configured to dispatch instructions in a first group of instructions from the second frame of instructions to functional units appropriate for the instructions in the first group of instructions in response to grouping bits of the instructions in the first group of instructions and in response to a mapping of the instructions in the first group of instructions to appropriate functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the second frame of instructions;

wherein the grouping bits of the instructions in the first group of instructions from the first 256-bit wide frame of instructions and the grouping bits of the instructions in the first group of instructions from the second 256 bit-wide frame of instructions are determined at compile time.

49. The apparatus of claim 48 wherein the instruction dispatching unit is also configured to dispatch instructions in a second group of instructions from the first frame of instructions to functional units appropriate for the instructions in the second group of instructions in response to grouping bits of the instructions in the second group of instructions and in response to a mapping of the instructions in the second group of instructions to appropriate functional units, wherein the mapping is determined in response to at least a portion of instruction data in each instruction in the second group of instructions from the first frame of instructions.

50. The apparatus of claim 48 wherein the first 256 bit-wide frame of instructions comprises a no operation.

51. The apparatus of claim 47 wherein the plurality of functional units comprise eight functional units including a floating-point unit.

52. The apparatus of claim 51 wherein an instruction in a group of instructions from the first frame of instructions comprises a floating point instruction.

53. The apparatus of claim 52 wherein the plurality of functional units also includes a functional unit configured to perform a load operation.

54. The apparatus of claim 51 wherein the plurality of functional units also includes a branch unit.

55. The apparatus of claim 54 wherein the first 256 bit-wide frame of instructions comprises exactly eight 32 bit-wide instructions.

56. The apparatus of claim 47 wherein more than two groups of instructions are packed within the first 256 bit-wide frame of instructions thereby reducing instruction code size.

57. The apparatus of claim 56 wherein the instruction dispatching unit is also configured to decode the instructions in the first group of instructions before dispatch to the appropriate functional units.

58. The apparatus of claim 57 wherein groups of instructions to be dispatched in parallel are not split across frames of instructions.

59. The apparatus of claim 56 wherein the grouping bits of the instructions in the first group of instructions from the first frame of instructions are specified at compile time in response to data dependency checking of the instructions in the first group of instructions from the first frame of instructions.

60. The apparatus of claim 56 wherein the instructions in the first instruction frame are stored in little-endian format.

61. The apparatus of claim 47

wherein the groups of instructions from the first frame of instructions comprise the first group of instructions, a second group of instructions, and a third group of instructions;

and

wherein a number of instructions in the first group of instructions is different from a number of instructions in the second group of instructions.

62. The apparatus of claim 61

wherein the groups of instructions from the first frame of instructions also comprise a fourth group of instructions;

and

wherein a number of instructions in the first group of instructions is different from a number of instructions in the fourth group of instructions.

63. The apparatus of claim 61 wherein the plurality of functional units includes at least one arithmetic logic unit.

67. The apparatus of claim 47 wherein a number of instructions in the first group of instructions is equal to a number of instructions in the second group of instructions.

68. The apparatus of claim 67 wherein the number of instructions in the first group of instructions is exactly one instruction.

69. The apparatus of claim 47 wherein the right-most instruction in the first frame of instructions is configured to store a branch operation.

70. An instruction memory comprises:

a first 256-bit wide frame of instructions comprising eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of variable numbers of instructions from the first frame of instructions, wherein the first frame of instructions comprise at least one group of instructions and comprise at most eight groups of instructions, wherein a number of instructions in the groups of instructions comprises at least one instruction and up to eight instructions, wherein a group of instructions are dispatched serially from left-to-right within the first frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel; and

a second 256 bit wide frame of instructions comprising eight 32 bit-wide instructions, each 32-bit wide instruction comprising 31 contiguous bits of instruction data and a one bit wide grouping bit, wherein grouping bits of the 32 bit-wide instructions are indicative of groups of variable numbers of instructions from the second frame of instructions, wherein the second frame of instructions comprise at least one group of instructions and comprise at most eight groups of instructions, wherein a number of instructions in the groups of instructions comprises at least one instruction and up to eight instructions, wherein a group of instructions are dispatched serially from left-to-right within the second frame of instructions, and wherein instructions within a group of instructions are dispatched in parallel;

wherein a first group of instructions from the first frame of instructions are dispatched to functional units appropriate for instructions in the first group in response to grouping bits of the instructions in the first group of instructions;

wherein a second group of instructions from the first frame of instructions are dispatched to functional units appropriate for instructions in the second group in response to grouping bits of the instructions in the second group of instructions;

wherein a first group of instructions from the second frame of instructions are dispatched to functional units appropriate for instructions in the first group in response to grouping bits of the instructions in the first group of instructions from the second frame of instructions; and

wherein the grouping bits of the instructions in the first frame of instructions and the grouping bits of the instructions in the second frame of instructions are determined at a time other than run-time.

71. The instruction memory of claim 70

wherein the first group of instructions from the second frame of instructions are dispatched only after all instructions in the first frame of instructions are dispatched.

72. The instruction memory of claim 71 wherein the grouping bits of the instructions from the first frame of instructions and the first group grouping bits of the instructions from the second frame of instructions are determined at compile time.

73. The instruction memory of claim 72

wherein the first group of instructions from the first frame of instructions are dispatched in response to a mapping of the instructions in the first group of instructions to appropriate functional units;

and

wherein the mapping of the instructions is determined in response to at least a portion of instruction data in each instruction in the first group of instructions from the first frame of instructions.

74. The instruction memory of claim 72 wherein an instruction in the first frame of instructions comprises a no-op instruction.

75. The instruction memory of claim 70 wherein functional units appropriate for instructions in the first group of instructions in the first frame of instructions comprise eight functional units.

76. The instruction memory of claim 75 wherein a functional unit appropriate for an instruction in the first frame of instructions comprises a floating point unit.

77. The instruction memory of claim 76 wherein an instruction in the first frame of instructions is sent to a functional unit that performs a store operation.

78. The instruction memory of claim 76 wherein a functional unit appropriate for an instruction in the first frame of instructions comprises an arithmetic logic unit.

79. The instruction memory of claim 78 wherein instructions in the first group of instructions from the first frame of instructions comprise two ALU instructions.

80. The instruction memory of claim 79 wherein an instruction in the second group of instructions from the first frame of instructions comprises a floating point instruction.

81. The instruction memory of claim 80 wherein an instruction from the first frame of instructions comprises a branch instruction.

82. The instruction memory of claim 70 wherein more than two groups of instructions are packed within the first 256 bit-wide frame of instructions thereby reducing instruction code size.

83. The instruction memory of claim 82 wherein the instructions in the first group of instructions are decoded prior to dispatch to the appropriate functional units.

84. The instruction memory of claim 83 wherein the instructions in the first group of instructions in the first frame of instructions are checked for data dependency at compile time.

85. The instruction memory of claim 83 wherein instructions stored in the first frame of instructions and stored in the second frame of instructions are not grouped into a single group of instructions.

86. The instruction memory of claim 82 wherein the instructions in the first instruction frame and the instructions in the second instruction are stored in little-endian format.

87. The instruction memory of claim 70 wherein the first group of instructions and the second group of instructions are packed into the first 256 bit-wide frame of instructions to reduce a number of no-operations in the first 256 bit-wide frame of instructions.

88. The instruction memory of claim 87 wherein a number of instructions in the first group of instructions is identical to a number of instructions in the second group of instructions.

89. The instruction memory of claim 88

wherein the first frame of instructions also comprise a third group of instructions;

and

wherein a number of instructions in the third group of instructions comprises more than one instruction.

90. The instruction memory of claim 89 wherein an instruction in the first group of instructions from the first frame of instruction specifies at least one source register and one destination register.