Method for applying instructions to microprocessor in test mode
First Claim
1. A method of applying instructions to a microprocessor during test mode, said method comprising:
- a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;
b) bypassing a first memory coupled to said microprocessor and forcing said microprocessor to execute instructions from an instruction queue;
c) said test controller filling said instruction queue with instructions to be executed, said instructions originating from a test interface; and
d) executing instructions from a second memory coupled to said microprocessor.
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Accused Products
Abstract
A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.
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Citations
23 Claims
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1. A method of applying instructions to a microprocessor during test mode, said method comprising:
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a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;
b) bypassing a first memory coupled to said microprocessor and forcing said microprocessor to execute instructions from an instruction queue;
c) said test controller filling said instruction queue with instructions to be executed, said instructions originating from a test interface; and
d) executing instructions from a second memory coupled to said microprocessor. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An architecture for applying instructions to a microprocessor during test mode, said architecture comprising:
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a microprocessor coupled to a bus;
an instruction queue coupled to said microprocessor;
a test controller coupled to said bus, said test controller operable to load instructions received from a test interface into said instruction queue; and
a first memory coupled to said microprocessor, said first memory comprising pre-determined test instructions. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14)
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15. A method of applying instructions to a microprocessor during test mode, said method comprising:
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a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;
b) said test controller transferring to a queue an instruction to be executed in said microprocessor; and
c) said instruction causing at least one test instruction from a first memory to be executed by said microprocessor, said first memory comprising a plurality of pre-determined test instructions. - View Dependent Claims (16, 17, 18, 19)
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20. A method of applying instructions to a microprocessor during test mode, said method comprising:
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a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;
b) said test controller transferring to a queue an instruction to be executed in said microprocessor;
c) said instruction causing at least one test instruction from a first memory to be executed by said microprocessor, said first memory comprising a plurality of test instructions; and
d) switching execution between instructions in said queue and said first memory, wherein said microprocessor switches between executing instructions originating from a test interface and said test instructions. - View Dependent Claims (21, 22, 23)
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Specification