Method for applying instructions to microprocessor in test mode

• US 6,892,322 B1
• Filed: 10/05/2001
• Issued: 05/10/2005
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): MASKULINSKI, MICHAEL C
• Application Number:
  US09/972,319
• Time in Patent Office: 1,313 Days
• Field of Search: 714/30, 714/31
• US Class Current: 714/30
• CPC Class Codes: G06F 11/2236 to test CPU or processors

Abstract

A method for applying instructions to a microprocessor during test mode is disclosed. In one embodiment of the present invention, first a test mode is entered, establishing the microprocessor as a slave and a test controller as a master. Then, the test controller fills an instruction queue with instructions to be executed. The instructions originate from a test interface. A memory, such as a program flash, coupled to the microprocessor is bypassed; thus, the microprocessor is forced to execute instructions from the instruction queue. In another embodiment, the test controller transfers to the instruction queue an instruction to be executed in the microprocessor. Then, the instruction causes instructions from a supervisory memory to be executed by the microprocessor. The supervisory memory comprises pre-determined test instructions.

Claims

1. A method of applying instructions to a microprocessor during test mode, said method comprising:

a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;

b) bypassing a first memory coupled to said microprocessor and forcing said microprocessor to execute instructions from an instruction queue;

c) said test controller filling said instruction queue with instructions to be executed, said instructions originating from a test interface; and

d) executing instructions from a second memory coupled to said microprocessor.

2. The method of claim 1 wherein said test interface is serial.

3. The method of claim 1 wherein said second memory contains a set of pre-determined test instructions.

4. The method of claim 3 further comprising:

e) switching execution between instructions in said instruction queue and said second memory.

5. The method of claim 3 further comprising:

e) said test controller transferring an instruction to said instruction queue, said instruction causing said microprocessor to execute instructions from said second memory instead of said instruction queue.

6. The method of claim 1 wherein said first memory is for holding instructions to be executed by said microprocessor when not in said test mode.

7. An architecture for applying instructions to a microprocessor during test mode, said architecture comprising:

a microprocessor coupled to a bus;

an instruction queue coupled to said microprocessor;

a test controller coupled to said bus, said test controller operable to load instructions received from a test interface into said instruction queue; and

a first memory coupled to said microprocessor, said first memory comprising pre-determined test instructions.

8. The architecture of claim 7, further comprising:

a second memory comprising instructions to be run when not in said test mode, said architecture operable to bypass said second memory when in said test mode.

9. The architecture of claim 8, wherein said test controller is not operable to access said second memory.

10. The architecture of claim 8, wherein said second memory comprises a program flash memory.

11. The architecture of claim 7, wherein said test controller is operable to force execution of instructions in said microprocessor between said instruction queue and said first memory by transferring a first instruction to said instruction queue.

12. The architecture of claim 11, wherein said microprocessor is operable to cause a supervisory state to be entered upon receiving said first instruction from said instruction queue, wherein said microprocessor causes instructions from said first memory to be fed to said microprocessor.

13. The architecture of claim 12, further comprising a register coupled to said bus, said register writeable in said supervisory state and not writeable when otherwise in said test mode, wherein said register is testable when in said supervisory state.

14. The architecture of claim 7, wherein said microprocessor is further operable to allow said test controller to control the source of instructions for said microprocessor when a set of said pre-determined test instructions from said first memory have finished executing.

15. A method of applying instructions to a microprocessor during test mode, said method comprising:

a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;

b) said test controller transferring to a queue an instruction to be executed in said microprocessor; and

c) said instruction causing at least one test instruction from a first memory to be executed by said microprocessor, said first memory comprising a plurality of pre-determined test instructions.

16. The method of claim 15 further comprising:

d) bypassing a second memory coupled to said microprocessor and forcing said microprocessor to execute instructions from said queue, said second memory comprising program instructions to be run when not in said test mode.

17. The method of claim 15 further comprising:

d) entering a supervisory state in which instructions of said test instructions from said first memory are executed in said microprocessor.

18. The method of claim 15 further comprising:

d) said microprocessor causing at least one test instruction from said first memory to be fed to said microprocessor in a supervisory state.

19. The method of claim 18 further comprising:

e) writing to a register during said supervisory state, said register not writeable during said test mode when not in said supervisory state.

20. A method of applying instructions to a microprocessor during test mode, said method comprising:

a) entering a test mode establishing said microprocessor as a slave and a test controller as a master;

b) said test controller transferring to a queue an instruction to be executed in said microprocessor;

c) said instruction causing at least one test instruction from a first memory to be executed by said microprocessor, said first memory comprising a plurality of test instructions; and

d) switching execution between instructions in said queue and said first memory, wherein said microprocessor switches between executing instructions originating from a test interface and said test instructions.

21. The method of claim 20 further comprising:

e) bypassing a second memory coupled to said microprocessor and forcing said microprocessor to execute instructions from said queue, said second memory comprising program instructions to be run when not in said test mode.

22. The method of claim 20 further comprising:

entering a supervisory state in which instructions of said test instructions from said first memory are executed in said microprocessor.

23. The method of claim 22 further comprising:

writing to a register during said supervisory state, said register not writeable during said test mode when not in said supervisory state.