Discrete multi-tone (DMT) system and method that communicates a data pump data stream between a general purpose CPU and a DSP via a buffering scheme

• US 6,892,339 B1
• Filed: 09/20/1999
• Issued: 05/10/2005
• Est. Priority Date: 09/20/1999
• Status: Expired due to Term

• Current Assignee: Apple Inc.
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Gusler, Lee T., Zuckerman, Ronald M., Wilson, Jr., Joe L., Quirk, Patrick J., Polk, Jr., Charles E.
• Primary Examiner(s): Decady, Albert
• Assistant Examiner(s): CHAUDRY, MUJTABA M
• Application Number:
  US09/398,707
• Time in Patent Office: 2,059 Days
• Field of Search: 714/746, 714/758, 714/776, 718/100, 718/107, 718/104, 340/7.21, 370/241, 370/294, 710/22, 360/40, 360/46, 360/65, 360/51, 375/222
• US Class Current: 714/746
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27
• CPC Class Codes: H04L 1/08 by repeating transmission, e.g. Verdan system H04L1/1858 and H04L1/189 take precedence
• CPC Class Codes: H04L 2001/0094 Bus
• CPC Class Codes: H04L 27/2626 Arrangements specific to the transmitter only

Abstract

The apparatus and method herein splits the function of a digital subscriber line (DSL) modem data pump between a digital signal processor (DSP 106) and a general purpose host central processing unit (CPU 102). The DSP (106) handles all front end data pump processing such as interface to an analog front end (108 and 110), FFT processing, FEQ processing, QAM decoding, and bit formatting. The host CPU (102) handles all back end data pump processing such as DMT tone deordering, data deinterleaving, error detection and correcting, bit descrambling, CRC processing, and the like. In order to enable the DSP (106) and the CPU (102) to communicate with each other effectively, buffers (132) under the control of specialized buffer management methodology (FIG. 4) are used.

Claims

1. A modem apparatus comprising:

an analog interface for interfacing to a communication line;

a digital signal processor coupled to the analog interface, the digital signal processor being coupled performs frequency domain equalization (FEQ) operations, time domain equalization (TEQ) operations, fast fourier transform (FFT) operations, inverse fast fourier transform (iFFT) operations, and encoding/decoding operations on a serial stream of data provided through the analog interface, the digital signal processor having an output;

a data bus coupled to the output of the digital signal processor; and

a host central processing unit (CPU) coupled to the data bus for receiving packets of data from the digital signal processor, the host CPU performing error correction operations on the data within the packets of data,

wherein at least one operation performed by one of the digital signal processor and the host CPU can be dynamically reassigned to a different one of the digitial signal processor and the host CPU.

2. The modem apparatus of claim 1 wherein the host CPU also performs interleaving and/or deinterleaving operations to intermingle or separate two or more different data symbols.

3. The modem apparatus of claim 1 wherein the host CPU performs Reed Solomon encoding and/or decoding on the data within the data packets.

4. The modem apparatus of claim 3 wherein the host CPU performs cyclic redundancy check (CRC) operations on the data within the data packets.

5. The modem apparatus of claim 1 wherein the host CPU performs tone ordering and/or deordering on the data within the data packets.

6. The modem apparatus of claim 1 wherein the host CPU configures and processes ATM data for transmission within DMT data packets.

7. The modem apparatus of claim 1 wherein the digital signal processor performs QAM encoding and/or decoding operations.

8. A method for processing, the method comprising the steps of:

receiving a serial stream of data via a first processor;

performing time domain to frequency domain operations on serial stream of data to create digital values via the first processor;

performing frequency domain equalization on the digital values via the first processor;

decoding the digital values to a binary stream that is packaged into byte/word boundaries of the first processor;

providing the binary stream to a second processor;

deinterleaving data within the binary sream via the second processor; and

error code correcting and/or CRC processing the binary stream via the second processor,

wherein at least one step performed by one of the first and second processors can be dynamically reassigned to a different one of the first and second processors.

9. The method of claim 8 wherein the first processor ATM processes the binary stream to extract data from ATM cells.

10. The method of claim 9 wherein the first processor processes the binary stream to extract data from TCP/IP packets.

11. The method of claim 8 wherein both the first and second processors control buffers that are used to buffer the binary stream between the first processor and the second processor.

12. The method of claim 8 wherein steps performed by the first processor can be dynamically switched over to the second processor.

13. The method of claim 8 wherein steps performed by the second processor can be dynamically switched over to the first processor.

14. The method of claim 8 wherein processing in the second processor is involved only after a certain amount of the binary stream is provided from the second processor to the first processor.