Systems and methods for generating an artwork representation according to a circuit fabrication process

• US 6,892,374 B2
• Filed: 06/19/2002
• Issued: 05/10/2005
• Est. Priority Date: 06/19/2002
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Burden, David C., Biggio, Matthew L., Melli, Bruno P.
• Primary Examiner(s): Thompson, A. M.
• Assistant Examiner(s): ROSSOSHEK, YELENA
• Application Number:
  US10/174,674
• Publication Number:
  US 20030237072A1
• Time in Patent Office: 1,056 Days
• Field of Search: 716 2- 6, 716 10- 13, 716/16, 716/17, 716/19, 717/131, 713/2, 710/305, 707/9, 707/100, 703/15, 703/23, 702/188, 355/86, 250/492.1, 101/463.1
• US Class Current: 716/55
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

In one embodiment, the present invention relates to a system for generating an artwork representation according to a circuit fabrication process. The system comprises a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of the plurality of circuit cells is defined by a sub-mask for a respective logical device according to the circuit fabrication process; an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logical devices and the cell library; and an artwork generator that generates an artwork representation that defines a mask for etching of the generated circuit layout according to the circuit fabrication process.

Claims

1. A system for generating an artwork representation according to a circuit fabrication process, comprising:

a cell library that stores at least dimensional information associated with a plurality of circuit cells, wherein each of said plurality of circuit cells is defined by a sub-mask for a respective logic device according to said circuit fabrication process;

an instance placement engine that generates a circuit layout that is defined by at least a specification file specifying an arrangement of logic devices and said cell library, wherein said instance placement engine calculates positions of logic devices in said circuit layout by separating adjacent logic devices identified in said specification file according to dimensional information stored in said cell library; and

an artwork generator that generates an artwork representation that defines a mask for etching of said generated circuit layout according to said circuit fabrication process.

2. The system of claim 1 wherein said specification file is a text file.

3. The system of claim 2 further comprising:

a parser that is operable to parse said text file.

4. The system of claim 1 wherein said instance placement engine is operable to identify circuit layout commands defining relative positioning of logic devices.

5. The system of claim 1 wherein said instance placement engine is operable to identify logic devices specified in said text file.

6. The system of claim 1 wherein said instance placement engine is operable to identify block definitions which specify repeatable arrangements of logic devices.

7. The system of claim 1 further comprising:

a wiring information library that specifies criteria for interconnection of circuit cells according to said circuit fabrication process;

wherein said artwork generator is operable to generate said artwork representation to include wiring interconnections defined in part by said specification file and said wire information library.

8. The system of claim 7 wherein said criteria for interconnection of circuit cells comprises a minimum wire size.

9. The system of claim 8 wherein said specification file defines starting and ending points of wires utilized to interconnect said logic devices.

10. The system of claim 1 wherein said artwork representation is a binary file.

11. A method for generating an artwork representation according to a circuit fabrication process, comprising:

receiving a specification file defining an arrangement of logic device;

accessing a cell library to retrieve circuit cell dimensional information defined by sub-masks of said logic devices according to said circuit fabrication process; and

generating an artwork representation of a circuit according to said circuit fabrication process utilizing at least said specification file and said circuit cell dimensional information, wherein said generating calculates positions of logic devices by separating adjacent logic devices identified in said specification file according to cell dimensional information stored in said cell library.

12. The method of claim 11 wherein said specification file is a text file.

13. The method of claim 12 further comprising:

identifying circuit layout commands defining relative positioning of logic devices.

14. The method of claim 12 further comprising:

identifying logic devices specified in said text file.

15. The method of claim 12 further comprising:

identifying block definitions which specify repeatable arrangements of logic devices.

16. The method of claim 11 wherein said artwork representation is a binary file.

17. The method of claim 11 further comprising:

generating a circuit mask from said artwork representation.

18. The method of claim 11 further comprising:

fabricating circuits utilizing said circuit mask.

19. The method of claim 11 further comprising:

accessing a wire information library to obtain wiring information, wherein said wire information library comprises criteria for interconnection of logic devices according to said circuit fabrication process; and

generating wire interconnections in said artwork from at least said specification file and said wiring information.

20. The system of claim 11 wherein said specification file defines starting and ending points of wires utilized to interconnect said logic devices.

21. A system for generating an artwork representation according to a circuit fabrication process, comprising:

means for storing at least dimensional information associated with a plurality of circuit cells, wherein each of said plurality of circuit cells is defined by a sub-mask for a respective logic device according to said circuit fabrication process;

means for generating a circuit layout that is defined by at least a specification file specifying an arrangement of logic devices and said means for storing, wherein said means for generating calculates positions of logic devices in said circuit layout by separating adjacent logic devices identified in said specification file according to dimensional information stored in said means for storing; and

means for generating an artwork representation that defines a mask for etching of said generated circuit layout according to said circuit fabrication process.

22. The system of claim 21 wherein said specification file is a text file.

23. The system of claim 22 further comprising:

means for parsing said text file.

24. The system of claim 21 wherein means for generating a circuit layout is operable to identify circuit layout commands defining relative positioning of logic devices.

25. The system of claim 21 wherein means for generating a circuit layout is operable to identify logic devices specified in said text file.

26. The system of claim 21 wherein means for generating a circuit layout is operable to identify block definitions which specify repeatable arrangements of logic devices.

27. The system of claim 21 further comprising:

means for storing criteria for interconnection of circuit cells according to said circuit fabrication process;

wherein said means for generating an artwork representation is operable to generate said artwork representation to include wiring interconnections defined in part by said specification file and said means for storing criteria for interconnection.

28. The system of claim 27 wherein said criteria for interconnection of circuit cells comprises a minimum wire size.

29. The system of claim 28 wherein said specification file defines starting and ending points of wires utilized to interconnect said logic devices.

30. A system for designing a circuit, comprising:

a cell library that stores dimensional information associated with a plurality of circuit cells, wherein each of said circuit cells is defined by a sub-mask for a respective logic device according to a circuit fabrication process;

a specification file defining an arrangement of logic devices within said circuit using fixed relative positions that are independent of said circuit fabrication process, wherein said specification file is a high-level user editable file; and

an instance placement engine that generates a circuit layout that is defined by said specification file and said cell library.

31. The system of claim 30 wherein said specification file includes statements defining a repeatable block of logic devices.

32. The system of claim 31 wherein said statements defining a repeatable block of logic devices are implemented using an object oriented data structure.

33. The system of claim 30 wherein said specification file comprises statements indicating a termination of a row of logic devices.

34. The system of claim 30 wherein said specification file comprises statements defining an orientation, a width, and a layer of a track segment within said circuit.

35. The system of claim 30 further comprising:

a graphical user interface (GUI) process for presenting a graphical representation of said circuit and for receiving user input to place circuit elements on said graphical representation, wherein said GUI interface process autonomously modifies said specification file in response to receiving said user input.

36. A method for designing a circuit, comprising:

storing dimensional information, in a cell library, associated with a plurality of circuit cells, wherein each of said circuit cells is defined by a sub-mask for a respective logic device according to a circuit fabrication process;

creating a user-editable specification file according to statements of a high-level circuit description language, wherein said specification file defines an arrangement of logic devices within said circuit using fixed relative positions that are independent of said circuit fabrication process; and

generating a circuit layout by placing logic devices within said circuit according to said circuit fabrication process using said specification file and said cell library.

37. The method of claim 36 wherein said creating said specification file comprises:

defining repeatable blocks of logic devices according to selected statements of said high-level circuit description language.

38. The method of claim 36 wherein said high-level circuit description language is an object oriented language.

39. The method of claim 36 wherein specification file comprises statements defining orientation, width, and layer characteristics of track segments within said circuit.