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Layout to minimize gate orientation related skew effects

  • US 6,893,925 B2
  • Filed: 07/21/2003
  • Issued: 05/17/2005
  • Est. Priority Date: 08/30/1999
  • Status: Expired due to Term
First Claim
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1. A method of making a symmetric transistor device comprising:

  • depositing a first conductive layer on a substrate, the first conductive layer forming an even number of transistor legs, laid out in an intersecting pattern, forming a bilaterally symmetric base;

    doping the substrate to form source and drain regions and non-diffused areas around the intersections of the transistor legs; and

    forming a plurality of transistors defined by a portion of a transistor leg forming a gate and the source and drain areas on either side of the leg forming a source and a drain.

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