Layout to minimize gate orientation related skew effects

• US 6,893,925 B2
• Filed: 07/21/2003
• Issued: 05/17/2005
• Est. Priority Date: 08/30/1999
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Bates, Jeffrey W., Kiss, Stephen W.
• Primary Examiner(s): Smith, Matthew
• Assistant Examiner(s): Malsawma, Lex H.
• Application Number:
  US10/624,831
• Publication Number:
  US 20040019865A1
• Time in Patent Office: 666 Days
• Field of Search: 438/213, 438/279, 438/323, 438/129
• US Class Current: 438/279
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body

Abstract

A method and apparatus for a driver layout is described. The layout includes an first number of gate lines arranged along a first axis and a second equal number of gates arranged along a second axis, such that the first set of gates lines is orthogonal to the second set of gates lines. The layout includes a total of N discrete transistors.

Claims

1. A method of making a symmetric transistor device comprising:

depositing a first conductive layer on a substrate, the first conductive layer forming an even number of transistor legs, laid out in an intersecting pattern, forming a bilaterally symmetric base;

doping the substrate to form source and drain regions and non-diffused areas around the intersections of the transistor legs; and

forming a plurality of transistors defined by a portion of a transistor leg forming a gate and the source and drain areas on either side of the leg forming a source and a drain.

2. The method of claim 1, further comprising:

depositing a silicon dioxide prior to depositing the first conductive layer.

3. The method of claim 1, wherein the intersecting pattern forms a tic-tac-toe pattern.

4. The method of claim 1, wherein the first conductive layer comprises polysilicon.

5. The method of claim 1, further comprising:

conductive interconnections between the source and drain areas to form a circuit.

6. The method of claim 1, wherein a first half of the transistors are oriented along a first axis and a second half of the transistors (N/2) oriented along a second axis orthogonal to the first half of the transistors.

7. The method of claim 6, wherein the minimum drawn W/L is used for each transistor leg.

8. A method of making a symmetric transistor device comprising:

depositing a first conductive layer on a substrate, the first conductive layer forming an even number of transistor legs, laid out in an intersecting pattern, forming a bilaterally symmetric base;

doping the substrate to form source and drain regions; and

forming a plurality of transistors defined by a portion of a transistor leg forming a gate and the source and drain areas on either side of the leg forming a source and a drain, so as to reduce skew effects due to mask alignment and gate orientation.

9. The method of claim 8, wherein a first half of the transistors are oriented along a first axis and a second half of the transistors (N/2) oriented along a second axis orthogonal to the first half of the transistors.

10. The method of claim 8, wherein variations in threshold voltage are reduced.