Fabrication of field effect transistor with shallow junctions using low temperature activation of antimony
First Claim
1. A method for fabricating a field effect transistor on an active device area of a semiconductor substrate, the method including the steps of:
- A. forming a gate dielectric and a gate electrode on said active device area of said semiconductor substrate;
B. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain extension junction and a source extension junction;
C. performing a low temperature thermal anneal process at a temperature less than about 950°
Celsius for activating said antimony (Sb) dopant within said drain and source extension junctions;
D. forming spacers at sidewalls of said gate dielectric and said gate electrode;
E. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain contact junction and a source contact junction having a deeper depth than said drain and source extension junctions;
F. performing a low temperature thermal anneal process at a temperature less than about 950°
Celsius for activating said antimony (Sb) dopant within said drain and source contact junctions; and
wherein said steps D, E, and F are performed after said step A and before said steps B and C such that said drain and source contact junctions are formed before said drain and source extension junctions in a disposable spacer process with an additional step of;
G. removing said spacers from said sidewalls of said gate dielectric and gate electrode after said steps E and F and before said steps B and C.
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Accused Products
Abstract
For fabricating a field effect transistor on an active device area of a semiconductor substrate, a gate dielectric and a gate electrode are formed on the active device area of the semiconductor substrate. Antimony (Sb) dopant is implanted into exposed regions of the active device area of the semiconductor substrate to form at least one of drain and source extension junctions and/or drain and source contact junctions. A low temperature thermal anneal process at a temperature less than about 950° Celsius is performed for activating the antimony (Sb) dopant within the drain and source extension junctions and/or drain and source contact junctions. In one embodiment of the present invention, the drain and source contact junctions are formed and thermally annealed before the formation of the drain and source extension junctions in a disposable spacer process for further minimizing heating of the drain and source extension junctions. In another embodiment of the present invention, the drain and source extension junctions and/or the drain and source contact junctions are formed to be amorphous before the thermal anneal process. In that case, a SPE (solid phase epitaxy) activation process in performed for activating the antimony (Sb) dopant within the amorphous drain and source extension junctions and/or the amorphous drain and source contact junctions at a temperature less than about 650° Celsius.
16 Citations
14 Claims
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1. A method for fabricating a field effect transistor on an active device area of a semiconductor substrate, the method including the steps of:
-
A. forming a gate dielectric and a gate electrode on said active device area of said semiconductor substrate;
B. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain extension junction and a source extension junction;
C. performing a low temperature thermal anneal process at a temperature less than about 950°
Celsius for activating said antimony (Sb) dopant within said drain and source extension junctions;
D. forming spacers at sidewalls of said gate dielectric and said gate electrode;
E. implanting antimony (Sb) dopant into exposed regions of said active device area of said semiconductor substrate to form a drain contact junction and a source contact junction having a deeper depth than said drain and source extension junctions;
F. performing a low temperature thermal anneal process at a temperature less than about 950°
Celsius for activating said antimony (Sb) dopant within said drain and source contact junctions; and
wherein said steps D, E, and F are performed after said step A and before said steps B and C such that said drain and source contact junctions are formed before said drain and source extension junctions in a disposable spacer process with an additional step of;
G. removing said spacers from said sidewalls of said gate dielectric and gate electrode after said steps E and F and before said steps B and C. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification
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- Resources
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Current AssigneeAdvanced Micro Devices, Inc.
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Original AssigneeAdvanced Micro Devices, Inc.
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InventorsYu, Bin, Wang, HaiHong
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Primary Examiner(s)MENZ, LAURA MARY
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Application NumberUS10/161,452Time in Patent Office1,082 DaysField of Search438/305, 438/308, 438/303, 438/301, 438/231, 438/528, 438/795, 438/14, 438/197, 438/199, 438/306, 438/307, 438/486, 438/487, 438/509, 438/508, 438/530, 438/535, 438/798US Class Current438/305CPC Class CodesH01L 21/26513 of electrically active speciesH01L 29/665 using self aligned silicida...H01L 29/6653 using the removal of at lea...H01L 29/66598 forming drain [D] and light...
