Floating gate memory cells utilizing substrate trenches to scale down their size

• US 6,894,343 B2
• Filed: 05/18/2001
• Issued: 05/17/2005
• Est. Priority Date: 05/18/2001
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Harari, Eliyahou, Samachisa, George, Yuan, Jack H.
• Primary Examiner(s): Flynn, Nathan J.
• Assistant Examiner(s): Quinto, Kevin
• Application Number:
  US09/860,704
• Publication Number:
  US 20030209751A1
• Time in Patent Office: 1,460 Days
• Field of Search: 257/314, 257/315, 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322, 257/323, 257/329, 257/375, 257/324
• US Class Current: 257/319
• CPC Class Codes: H10B 41/23 with source and drain on different levels, e.g. with sloping channels
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Several embodiments of flash EEPROM split-channel cell arrays are described that position the channels of cell select transistors along sidewalls of trenches in the substrate, thereby reducing the cell area. Select transistor gates are formed as part of the word lines and extend downward into the trenches with capacitive coupling between the trench sidewall channel portion and the select gate. In one embodiment, trenches are formed between every other floating gate along a row, the two trench sidewalls providing the select transistor channels for adjacent cells, and a common source/drain diffusion being positioned at the bottom of the trench. A third gate provides either erase or steering capabilities. In another embodiment, trenches are formed between every floating gate along a row, a source/drain diffusion extending along the bottom of the trench and upwards along one side with the opposite side of the trench being the select transistor channel for a cell. Techniques for manufacturing such flash EEPROM split-channel cell arrays are also described.

Claims

1. In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by a floating gate and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising:

trenches provided in the semiconductor substrate as part of the cells, said second channel segment of the individual cells being provided along a sidewall of one of the trenches and the select sate being positioned in the trench, and

elongated third gates extending across the array along and capacitively coupled with floating gates, wherein the elongated third gates are erase gates that have lengths extending in a direction along rows of floating gates and which are individually positioned between adjacent rows of floating gates in a manner to have capacitive coupling with edges of the floating gates of at least one of said adjacent rows.

3. The memory structure of either claims 1 and 2, wherein one of the trenches is positioned between each of adjacent columns of floating gates, and the source and drain diffusions are positioned at the bottom of the trenches and extend upwards along a sidewall of the trenches opposite to the second channel portion.

4. The memory structure of either one of claim 1 and 2, wherein one of the trenches is positioned between every other column of floating gates across the array, and the source and drain diffusions are positioned between the columns of floating gates at the bottom of the trenches and along the surface of the substrate.

2. In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by a floating gate and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising:

trenches provided in the semiconductor substrate as part of the cells, said second channel segment of the individual cells being provided along a sidewall of one of the trenches and the select gate being positioned in the trench, and

elongated third gates extending across the array along and capacitively coupled with floating gates, wherein the elongated third gates are steering gates that have lengths extending across columns of floating gates and are individually positioned to have capacitive coupling with top surfaces of the floating gates of at least one column and underlie said word lines.

5. In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by a floating gate and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising:

trenches provided in the semiconductor substrate as cart of the cells, said second channel segment of the individual cells being provided along a sidewall of one of the trenches and the select gate being positioned in the trench, and

elongated third gates extending across the array along and capacitively coupled with floating gates,

wherein one of the trenches is positioned between each of adjacent columns of floating gates, and the source and drain diffusions are positioned at the bottom of the trenches and extend upwards along a sidewall of the trenches opposite to the second channel portion.

6. In an array of non-volatile memory cells formed in rows and columns on a semiconductor substrate with elongated source and drain diffusions extending between columns of cells and word lines extending across rows of cells, wherein individual cells have a first channel segment between adjacent source and drain diffusions in the substrate that is controlled by a floating gate and a second channel segment that is controlled by a select gate portion of one of the word lines, an improved structure comprising:

trenches provided in the semiconductor substrate as part of the cells, said second channel segment of the individual cells being provided along a sidewall of one of the trenches and the select gate being positioned in the trench, and

elongated third gates extending across the array along and capacitively coupled with floating gates,

wherein one of the trenches is positioned between every other column of floating gates across the array, and the source and drain diffusions are positioned between the columns of floating gates at the bottom of the trenches and along the surface of the substrate.

7. An array of non-volatile memory cells on a semiconductor substrate, comprising:

elongated source and drain diffusions having their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,

an array of floating gates arranged in columns extending in the first direction and rows extending in the second direction, individual memory cells having one edge of their floating gates positioned over one of the diffusions,

trenches in the substrate adjacent opposite edges of the floating gates in the second direction, said trenches containing another one of the diffusions,

elongated control gates having lengths extending in the second direction along rows of floating gates and being capacitively coupled with the sidewalls of the trenches that are positioned immediately adjacent the floating gates, and

elongated erase gates having lengths extending in the second direction across the array along and capacitively coupled with rows of floating gates.

8. The memory cell of claim 7, wherein the source and drain diffusions are formed in the bottoms of the trenches and on a surface of the semiconductor substrate.

9. The memory cell array of claim 7, wherein the source and drain diffusions are formed in a bottom and one side of the trenches.

10. An array of non-volatile memory cells on a semiconductor substrate, comprising:

elongated source and drain diffusions having their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,

an array of floating gates arranged in columns extending in the first direction and rows extending in the second direction, individual memory cells having one edge of their floating gates positioned over one of the diffusions,

trenches in the substrate adjacent opposite edges of the floating gates in the second direction, said trenches containing another one of the diffusions,

elongated word lines having lengths extending in the second direction over rows of floating gates and having select gates capacitively coupled with the sidewalls of the trenches that are positioned immediately adjacent the floating gates, and

elongated steering gates having lengths extending in the first direction across the array over and capacitively coupled with columns of floating gates.

11. The memory cell array of claim 10, wherein the source and drain diffusions are formed in the bottoms of the trenches and on a surface of the semiconductor substrate.

12. The memory cell array of claim 10, wherein the source and drain diffusions are formed in a bottom and one side of the trenches.

13. An array of non-volatile memory cells on a semiconductor substrate, comprising:

elongated trenches formed in the substrate with their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,

elongated source and drain diffusions with their lengths extending in the first direction and being spaced apart in the second direction such that first alternate diffusions are formed in the substrate along a bottom of individual trenches and that second alternate diffusions are formed in the substrate along a top surface thereof,

an array of floating gates spaced apart across the top surface of the substrate in the first direction and individually spanning between a trench and substrate surface diffusion in the second direction without extending downward into a trench,

elongated word lines having lengths extending in the second direction over floating gates and being spaced apart in the first direction, said word lines having select gates extending downward into the trenches to capacitively couple with opposing sidewalls of the trenches, and elongated third gates extending across the array and individually being capacitive coupled with a plurality of floating gates.

14. The memory cell array of claim 13, wherein the elongated third gates are erase gates having lengths extending in the second direction and which are spaced apart in the first direction, said third gates having capacitive coupling with edges of adjacent floating gates.

15. The memory cell array of claim 13, wherein the elongated third gates are steering gates that have lengths extending in the first direction and which are spaced apart in the second direction, said third gates having capacitive coupling with top surfaces of floating gates over which they pass.

16. An array of non-volatile memory cells on a semiconductor substrate, comprising:

elongated trenches formed in the substrate with their lengths extending in a first direction and being spaced apart in a second direction, the first and second directions being orthogonal to each other,

elongated source and drain diffusions with their lengths extending in the first direction being formed in the substrate along a bottom and extending upward along one sidewall of the individual trenches to a top surface of the substrate but being absent from an opposite sidewall of the individual trenches, said one sidewall of the trenches facing the same direction, an array of floating gates spaced apart across the top surface of the substrate in the first direction and spanning between the trenches in the second direction without extending downward into the trenches, and

elongated word lines having lengths extending in the second direction over floating gates and being spaced apart in the first direction, said word lines having select gates extending downward into the trenches to capacitively couple with said opposite trench sidewalls.

17. The memory cell array of claim 16, which additionally comprises elongated steering gates having lengths extending in the first direction and being spaced apart in the second direction, said steering gates extending under the word lines and over floating gates with capacitive coupling between the steering gates and the floating gates.

18. The memory cell array of claim 16, which additionally comprises elongated control gates having lengths extending in the second direction and being spaced apart in the first direction, said control gates being capacitively coupled with edges of floating gates along which the individual control gates are positioned.