Semiconductor device

• US 6,894,346 B2
• Filed: 08/13/2003
• Issued: 05/17/2005
• Est. Priority Date: 12/18/2002
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Onose, Hidekatsu, Watanabe, Atsuo
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): Nguyen, Joseph
• Application Number:
  US10/640,411
• Publication Number:
  US 20040119092A1
• Time in Patent Office: 643 Days
• Field of Search: 257/257, 257/256, 257263-266, 257134-136, 257/342, 257/394, 257 76- 77
• US Class Current: 257/329
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/808 with a PN junction gate , e.g. PN homojunction gate H01L29/7725, H01L29/775, H01L29/778, H01L29/806 take precedence

Abstract

A structure is provided that ensures a low on-resistance and a better blocking effect. In a lateral type SIT (Static Induction Transistor) in which a first region is used as a p⁺ gate and a gate electrode is formed on the bottom of the first region, the structure is built such that the p⁺ gate and an n⁺ source are contiguous. An insulating film is formed on the surface of an n⁻ channel, and an auxiliary gate electrode is formed on the insulating film. In addition, the auxiliary gate electrode and the source electrode are shorted.

Claims

1. A semiconductor device having a band gap of 2.0 eV or higher and having a pair of major surfaces, comprising:

a substrate having a low impurity-density first conductivity type;

a first region formed on a first major surface of said substrate and having a second conductivity type and a resistance lower than that of said substrate;

a control electrode formed under said first region;

a second region formed on a second major surface of said substrate and having the same conductivity type as, and a resistance lower than, that of said substrate;

a second electrode formed on said second region;

a third region formed on the second major surface of said substrate and having the same conductivity type as, and a resistance lower than, that of the substrate; and

a third electrode formed on said third region,

wherein a surface of said third region is at a level lower than a bottom of said second region and said third region is contiguous to a first region.

2. The semiconductor device according to claim 1, wherein said second region is formed such that it is exposed on a part of said second major surface.

3. The semiconductor device according to claim 1, wherein said third region is formed on a substrate region lowered from the bottom of said second region by removing said second major surface of the substrate in a part except said second region.

4. The semiconductor device according to claim 3, wherein a fourth electrode is formed via an insulating film on a surface of the lowered substrate and on a surface of said third region and wherein the third electrode and the fourth electrode are shorted.

5. The semiconductor device according to claim 3, wherein an insulating film is formed on a surface of the lowered substrate, wherein a fourth electrode is formed across the insulating film, and wherein said fourth electrode and said third electrode are shorted.