Apparatus and method for packaging circuits

• US 6,894,386 B2
• Filed: 04/08/2002
• Issued: 05/17/2005
• Est. Priority Date: 10/08/2001
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeung, Boon Suan, Poo, Chia Yong, Loo, Neo Yong, Koon, Eng Meow, Kwang, Chua Swee, Waf, Low Siu, Yu, Chan Min, Leng, Ser Bok, Chung, So Chee, Seng, Ho Kwok
• Primary Examiner(s): Parekh, Nitin
• Application Number:
  US10/118,576
• Publication Number:
  US 20030067001A1
• Time in Patent Office: 1,135 Days
• Field of Search: 257/730, 257/692, 257/693, 257/690, 257/773, 257/786, 257/787, 257/698, 257/620, 257/622, 438460-462, 438/113
• US Class Current: 257/730
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02311 Additive methods
• CPC Class Codes: H01L 2224/02313 Subtractive methods
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02371 connecting the bonding area on a surface of the semiconductor or solid-state body with another surface of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/02379 Fan-out arrangement
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03622 using masks
• CPC Class Codes: H01L 2224/039 Methods of manufacturing bonding areas involving a specific sequence of method steps
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/05569 the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/056 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/08237 : the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/80357 : being flush with the surface
• CPC Class Codes: H01L 2224/804 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/80898 : Press-fitting, i.e. pushing the parts together and fastening by friction, e.g. by compression of one part against the other
• CPC Class Codes: H01L 2224/93 : Batch processes
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/08 : of an individual bonding area
• CPC Class Codes: H01L 24/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 24/93 : Batch processes
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 : Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/05042 : Si3N4
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H10B 99/22 : including field-effect components

Abstract

Methods for forming an edge contact on a die and edge contact structures are described. The edge contacts on the die do not increase the height of the die. The edge contacts are positioned on the periphery of a die. The edge contacts are positioned in the saw streets. Each edge contact is connected to one bond pad of each die adjacent the saw street. The edge contact is divided into contacts for each adjacent die when the dies are separated. In an embodiment, a recess is formed in the saw street. In an embodiment, the recess is formed by scribing the saw street with a mechanical cutter. The recess is patterned and contact material is deposited to form the edge contacts.

Claims

1. An integrated circuit die, comprising:

a main body including a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the main body;

an edge contact at the peripheral edge surface;

a line connecting the bond pad to the edge contact; and

wherein the edge contact is beneath the top layer.

2. The integrated circuit die of claim 1, wherein the main body includes an integrated circuit therein electrically connected to the bond pad.

3. The integrated circuit die of claim 1, wherein the edge contact is above a bottom surface of the bottom layer such that the edge contact does not increase a height of the die.

4. The integrated circuit of claim 1, wherein the edge contact includes at least one of copper, gold, or silver.

5. The integrated circuit of claim 1, wherein the bond pad is at the top layer.

6. An integrated circuit die, comprising:

a main body including a top layer and a bottom layer, a distance between a top surface of the top layer and a bottom surface of the bottom layer defines a first height, the main body including a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the top layer;

an edge contact at the peripheral edge surface, the edge contact having a second height, the second height being less than the first height; and

a line connecting the bond pad to the edge contact.

7. The integrated circuit die of claim 6, wherein the edge contact includes a metallic coating.

8. The integrated circuit die of claim 7, wherein the metallic coating includes at least one of silver and gold.

11. The integrated circuit die of claim 6, wherein the main body includes an integrated circuit therein electrically connected to the bond pad.

9. An integrated circuit die, comprising:

a main body including a top layer and a bottom layer, a distance between a top surface of the top layer and a bottom surface of the bottom layer defines a first height, the main body including a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the top layer;

an edge contact at the peripheral edge surface, the edge contact having a second height, the second height being less than the first height;

a line connecting the bond pad to the edge contact; and

wherein the main body includes an insulative coating on the bond pad and line.

10. The integrated circuit die of claim 9, wherein the insulative coating includes at least one of benzocyclobutenes and polymides.

12. A wafer, comprising:

a plurality of dies,

saw streets intermediate adjacent pairs of the plurality of dies,

wherein at least one pair of adjacent dies have a first bond pad on a first of the pair of adjacent dies and a second bond pad on a second of the pair of adjacent dies,

an edge contact is recessed in the saw street intermediate the first of the pair of adjacent dies and the second of the pair of adjacent dies, wherein the edge contact does not extend above top surfaces of the at least one pair of adjacent dies;

a first line extends from the first bond pad to the edge contact, and

a second line extends from the second bond pad to the edge contact.

13. The wafer of claim 12, wherein the first die and the second die have essentially coplanar top surfaces.

14. The wafer of claim 12, wherein the first die and the second die have essentially coplanar bottom surfaces, and the edge contact does not extend below the bottom surfaces.

15. The wafer of claim 12, wherein the first line and the second line are linearly aligned.

16. The wafer of claim 12, wherein the first line extend essentially perpendicular to the lengthwise direction of the saw street.

17. The wafer of claim 12, wherein the first bond pad is positioned essentially in the center of the first of the pair of adjacent dies.

18. The wafer of claim 12, wherein the first die is separated from the second die along the saw street such that a first part of the edge contact remains on the first die and a second part of the edge contact remains on the second die.

19. An integrated circuit die, comprising:

a main body including a top layer, a bottom layer, and a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the main body;

an edge contact at the peripheral edge surface, the edge contact having an outer peripheral surface remote from the main body and an inner surface adjacent the main body, wherein the outer peripheral surface is essentially coplanar with the edge surface of the main body; and

a line connecting the bond pad to the edge contact.

20. The integrated circuit die of claim 19, wherein the bond pad is at the top layer.

21. The die of claim 19, wherein the edge contact is beneath the top layer.

22. A land pattern, integrated circuit package, comprising:

a die including a top surface, a bottom surface and a peripheral surface extending between the top surface and the bottom surface;

an encapsulant substantially enclosing the die;

at least one edge contact on the peripheral surface, wherein the at least one edge contact extends outside the encapsulant.

23. The package of claim 22, wherein the at least one edge contact has a height essentially equal to the peripheral surface.

24. The package of claim 22, wherein the die includes at least one bond pad and at least one line connecting the bond pad to the at least one edge contact.

25. The package of claim 22, wherein the at least one edge contact include a first part on the peripheral surface and a second part extending outwardly from the encapsulant.

26. The package of claim 22, wherein the at least one edge contact is beneath the top surface.

27. The package of claim 22, wherein the at least one edge contact is above the bottom surface such that the edge contact does not increase the height of the die.

28. An integrated circuit die, comprising:

a main body including a top layer and a bottom layer, a distance between a top surface of the top layer and a bottom surface of the bottom layer defines a first height, the main body including a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the top layer;

an edge contact at the peripheral edge surface, the edge contact having a second height, the second height being less than the first height;

a line connecting the bond pad to the edge contact;

wherein the top surface of the top layer is essentially planar, wherein the bottom surface of the bottom layer is essentially planar and essentially parallel to the top surface of the top layer, and wherein the edge contact extends perpendicular to the top surface of the top layer.

29. An integrated circuit die, comprising:

a main body including a top layer and a bottom layer, a distance between a top surface of the top layer and a bottom surface of the bottom layer defines a first height, the main body including a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the top layer;

an edge contact at the peripheral edge surface, the edge contact having a second height, the second height being less than the first height;

a line connecting the bond pad to the edge contact; and

wherein the top surface of the top layer is essentially planar, and wherein the edge contact extends perpendicular to the top surface of the top layer.

30. An integrated circuit die, comprising:

a main body including a top layer and a bottom layer, a distance between a top surface of the top layer and a bottom surface of the bottom layer defines a first height, the main body including a peripheral edge surface extending between the top layer and the bottom layer;

a bond pad on the top layer;

an edge contact at the peripheral edge surface, the edge contact having a second height, the second height being less than the first height;

a line connecting the bond pad to the edge contact;

wherein the bottom surface of the bottom layer is essentially planar, and wherein the edge contact extends perpendicular to the bottom surface of the bottom layer.