Scaleable integrated data processing device

• US 6,894,392 B1
• Filed: 06/02/1999
• Issued: 05/17/2005
• Est. Priority Date: 06/02/1998
• Status: Expired due to Fees

• Current Assignee: Thin Film Electronics ASA
• Original Assignee: Thin Film Electronics ASA
• Inventors: Nordal, Per-Erik, Leistad, Geirr I., Gudesen, Hans Gude
• Primary Examiner(s): Nelms, David
• Assistant Examiner(s): TRAN, MAI HUONG C
• Application Number:
  US09/463,900
• Time in Patent Office: 2,176 Days
• Field of Search: 257/777, 257/369, 257/373, 257/310, 257/544, 257/728
• US Class Current: 257/759
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/02689 using particle beams
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/76888 By rendering at least a portion of the conductor non conductive, e.g. oxidation
• CPC Class Codes: H01L 21/76894 using a laser, e.g. laser cutting, laser direct writing, laser repair
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 20/10 ROM devices comprising bipolar components
• CPC Class Codes: H10B 53/00 Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
• CPC Class Codes: H10K 71/00 Manufacture or treatment specially adapted for the organic devices covered by this subclass
• CPC Class Codes: H10K 71/50 Forming devices by joining two substrates together, e.g. lamination techniques

Abstract

A scaleable integrated data processing device, particularly a microcomputer, comprises a processing unit with one or more processors and a storage unit with one or more memories. The data processing device is provided on a carrier substrate (S) and comprises mutually adjacent substantially parallel layers (P, M, MP) stacked up on each other, the processing unit and the storage unit being provided in one or more such layers and the separate layers formed with a selected number of processors and memories in selected combinations. In each layer are provided horizontal electrical conducting structures which constitute electrical internal connections in the layer and besides each layer comprises further electrical conducting structures which provide electrical connections to other layers and to the exterior of the data processing device. The integrated data processing device has a scaleable architecture, such that it in principle can be configured with an almost unlimited processor and memory capacity. Particularly can the data processing device implement various forms of scaleable parallel architectures integrated with optimal interconnectivity in three dimensions.

Claims

1. A scaleable integrated data processing device, provided on a carrier substrate, comprising a processing unit having one or more processors, and a storage unit having one or more memories,

wherein the data processing device comprises mutually adjacent, substantially parallel stacked layers and the processing unit and the storage unit are provided in one or more of the substantially parallel stacked layers,

wherein each of the substantially parallel stacked layers comprises one or more processors and/or one or more memories, and electrical conducting structures which form internal electrical connections in the layer,

wherein each substantially parallel stacked layer is formed of a plurality of sublayers, having delimited portions which form dielectric, semiconducting or electrical conducting areas in the sublayer and the sublayer, in addition to at least one dielectric portion, having one or more semiconducting and/or electrical conducting portions,

wherein delimited portions with a given electrical property in each sublayer are provided in a registering relationship to one or more corresponding portions in at least one of the adjacent neighbor sublayers to form integrated circuit elements which extend vertically through one or more sublayers,

wherein the electrical conducting structures are formed by the electrical conducting portions in the sublayer and respectively extend horizontally in order to create horizontal electrical conducting structures or are provided in registering connection with corresponding electrical conducting portions in one or more adjacent sublayers, such that the electrical conducting structures integrated in the sublayers form three-dimensional electrical interconnecting networks in the layers and interconnect the circuit elements therein mutually in three dimensions, and

wherein additional electrical conducting structures in the data-processing device interconnect the layers mutually and/or the layers with the substrate and in order to create a connection to the exterior of the data processing device.

2. A scaleable integrated data processing device according to claim 1, wherein the sublayers in one or more of the substantially parallel stacked layers are realized in a technology which on a first level of a functional hierarchy configures functionally one or more of the layers as a combined processor and memory layer, or one or more the layers substantially as processor layers or one or more the layers substantially as memory layers.

3. A scaleable integrated data processing device according to claim 2, wherein the processing unit in a layer is configured functionally on a second level of the functional hierarchy as one or more processors or parts of one or more processors, at least one processor constituting a central processing unit or microprocessor in the data processing device, and possible further processors optionally being configured as control and/or communication processors respectively.

4. A scaleable integrated data processing device according to claim 3, wherein the central processing unit is configured functionally on a third level of the functional hierarchy as a parallel processor with several execution units working in parallel provided in one and the same layer or in two or more layers or in sublayers thereof to provide an optimal interconnection topology.

5. A scaleable integrated data processing device according to claim 3, wherein more than one central processing unit is provided, wherein each central processing unit is mutually interconnected and adapted for working in parallel and provided in one and the same layer or in two or more layers to provide an optimal interconnection topology.

6. A scaleable integrated data processing device according to claim 3, wherein the storage unit in a layer is configured functionally on the second level of the functional hierarchy as one or more memories or parts of one or more memories, at least one memory constituting a RAM and being connected with at least one control processing unit or microprocessor, and possible further memories optionally being configured as high-speed memories, ROMs, WORM, ERASABLE and REWRITEABLE respectively.

7. A scaleable integrated data processing device according to claim 6, wherein two or more RAMs are connected to a central processing unit and respectively assigned to two or more subunits in the central processing unit, RAMs and the subunits being distributed in selected combinations in one or more layers to provide an optimal interconnection topology.

8. A scaleable integrated data processing device according to claim 6, wherein two or more central processing units are provided which are connected with one or more common RAM or RAMs, and each central processing unit is provided in mutually adjacent layers, or distributed in selected combinations between two or more layers, and that the common RAM or RAMs are provided in selected combinations in one or more of the layers and/or in one or more memory layers adjacent to the latter or interfoliated there between to provide an optimal interconnection topology.

9. A scaleable integrated data processing device according to claim 6, wherein at least a part of the storage unit constitutes a mass memory, the mass memory optionally being configured as RAM, ROM, WORM, ERASABLE or REWRITEABLE or combinations thereof.

10. A scaleable integrated data processing device according to claim 2, wherein the data processing unit comprises several processor layers and several memory layers, and the memory layers, in order to reduce the signal paths there between and the processor layers, are interfoliated between the latter.

11. A scaleable integrated data processing device according to claim 1, wherein further electrical structures are provided as electrical edge connections on or over at least one side edge of one or more layers in order to contact electrical conducting structures in other layers and/or provide electrical connection between layers and substrate.

12. A scaleable integrated data processing device according to claim 1, wherein the further electrical conducting structures are provided as vertical conducting structures in one or more layers and form electrical connections in the cross-direction of the layers and perpendicular to their planes in order to contact electrical conducting structures in other layers and/or to provide electrical connection between the layers and substrate.

13. A scaleable integrated data processing device according to claim 1, wherein one or more layers are formed of an organic thin-film material, the organic thin-film material or materials selected from the group consisting of monomeric, oligomeric and polymeric organic materials and metal-organic complexes, and combinations thereof.

14. A scaleable integrated data processing device according to claim 13, wherein all layers are formed of organic thin-film material.

15. A scaleable integrated data processing device according to claim 1, wherein one or more layers are formed of inorganic thin-film material, the inorganic thin-film material or materials being selected from the group consisting of crystalline, polycrystalline and amorphous thin-film materials, and combinations thereof.

16. A scaleable integrated data processing device according to claim 1, wherein two or more layers are formed of both organic and inorganic thin-film materials or combinations thereof, the organic thin-film material or materials being selected from the group consisting of monomeric, oligomeric and polymer organic materials and metal-organic complexes, and combinations thereof, and the inorganic thin-film material or materials being selected from the group consisting of crystalline, polycrystalline and amorphous thin-film materials, and combinations thereof.

31. The scaleable integrated data processing device of claim 1, wherein one or more of the plurality of sublayers is formed from organic materials.

17. A data processing device, comprising:

a carrier substrate; and

a plurality of main layers formed above the carrier-substrate, wherein each main layer is one of a processor layer, a memory layer, or a combination layer, and wherein at least one main layer includes logic devices formed from organic materials.

18. The data processing device of claim 17, wherein the at least one main layer comprises a plurality of vertically stacked sublayers, wherein:

at least one sublayer includes at least one horizontally conducting structure for electrically connecting logic devices; and

at least one sublayer includes at least one vertically conducting portion for electrically connecting logic devices.

19. The data processing device of claim 18, wherein at least one vertically conducting structure is formed from aligned corresponding vertically conducting portions of at least two adjacent sublayers.

20. The data processing device of claim 18, wherein the logic devices of the at least one main layer are formed to extend vertically through at least one sublayer.

21. The data processing device of claim 18, wherein portions of an organic material layer of the at least one sublayer are configured to have varying mode and degree of electrical conductivity.

22. The data processing device of claim 21, wherein the organic material layer at least one of polymer molecules, aromatic molecules, polyaniline films, and polythienylene vinylene films.

23. The data processing device of claim 21, wherein the electrical conductivity of the organic material layer is accomplished through application of at least one of electrical fields, voltages, currents, photon radiation, and particle radiation.

24. The data processing device of claim 17, wherein a first main layer formed directly above the carrier substrate is formed from a plurality of sublayers, wherein at least one sublayer of the main layer is based on inorganic technology.

25. The data processing device of claim 24, wherein the at least one sublayer is based on silicon or on thin film technology.

26. The data processing device of claim 17, wherein a memory portion of at least one memory layer or at least one combination layer comprises:

a plurality of substantially parallel overlying electrodes;

a plurality of substantially parallel underlying electrodes, wherein the overlying and underlying electrodes intersect to form a matrix; and

a plurality of logic cells formed at the intersections of the matrix.

27. The data processing device of claim 26, wherein the underlying electrode is made from a material with a lower work function relative to the overlying electrode, and wherein at least one logic cell comprises:

a first polymer in contact with the underlying electrode;

a second polymer in contact with the overlying electrode; and

a third polymer formed between the first and second polymers, such that the first, second, and third polymers form a rectifying diode.

28. The data processing device of claim 27, wherein:

the first and second polymers are formed from polythiophene; and

the third polymer is formed from water-soluble polythiophene.

29. The data processing device of claim 26, wherein at least one logic cell is formed from ferroelectric material.

30. The data processing device of claim 26, wherein at least one logic cell is configured to store more than two levels of code.