DRAM refresh scheme with flexible frequency for active and standby mode
First Claim
1. A method for providing a dynamic random access memory, DRAM, refresh with a flexible refresh frequency for active and standby mode comprising the step of:
- providing a higher refresh frequency during active mode than for standby mode, wherein said higher refresh frequency during active mode allows faster restoration of cell data, which is degraded by capacitive coupling through selection and switching of one or more adjacent word lines, and wherein said refresh frequency during standby mode can be lowered since cell charge lost due to adjacent word line switching does not occur.
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Abstract
The present invention provides a method and an apparatus for DRAM refresh with different frequencies of refresh for active and standby mode. In addition, this invention utilizes different refresh frequencies during active and standby modes to optimize power dissipation and DRAM data integrity. The refresh frequency during active mode is higher than said refresh frequency during standby mode. The refresh frequency during active mode is higher than the prior art refresh frequency during active mode. The refresh frequency during standby mode is lower than the prior art refresh frequency during standby mode. The higher active mode refresh frequency allows the faster restoration of cell data, which is degraded by capacitive discharge coupling through the selection of adjacent word lines. The low standby mode refresh frequency provides a lower standby power dissipation which compensates for the higher active mode power dissipation caused by the higher active mode refresh frequency.
19 Citations
28 Claims
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1. A method for providing a dynamic random access memory, DRAM, refresh with a flexible refresh frequency for active and standby mode comprising the step of:
providing a higher refresh frequency during active mode than for standby mode, wherein said higher refresh frequency during active mode allows faster restoration of cell data, which is degraded by capacitive coupling through selection and switching of one or more adjacent word lines, and wherein said refresh frequency during standby mode can be lowered since cell charge lost due to adjacent word line switching does not occur. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. An apparatus for providing a dynamic random access memory, DRAM, refresh with a flexible refresh frequency for active and standby mode comprising:
a refresh clock with higher frequency during active mode than for standby mode, wherein said higher refresh frequency during active mode allows faster restoration of cell data, which is degraded by capacitive coupling through selection and switching of one or more adjacent word lines, and wherein said refresh frequency during standby mode can be lowered since cell charge lost due to adjacent word line switching does not occur. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28)
Specification