Multi-state memory

• US 6,894,926 B2
• Filed: 04/30/2003
• Issued: 05/17/2005
• Est. Priority Date: 08/07/1997
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Fong, Yupin Kawing, Guterman, Daniel C.
• Primary Examiner(s): Nguyen, Viet Q.
• Application Number:
  US10/427,602
• Publication Number:
  US 20040042294A1
• Time in Patent Office: 748 Days
• Field of Search: 365/185.03, 365/185.02, 365/185.09, 365/185.22, 365/185.29, 365/185.28, 365/185.21
• US Class Current: 365/185.03
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/76 using address translation or modifications
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/7885 Hot carrier injection from the channel
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Maximized multi-state compaction and more tolerance in memory state behavior is achieved through a flexible, self-consistent and self-adapting mode of detection, covering a wide dynamic range. For high density multi-state encoding, this approach borders on full analog treatment, dictating analog techniques including A to D type conversion to reconstruct and process the data. In accordance with the teachings of this invention, the memory array is read with high fidelity, not to provide actual final digital data, but rather to provide raw data accurately reflecting the analog storage state, which information is sent to a memory controller for analysis and detection of the actual final digital data.

Claims

1. A storage device comprising:

a non-volatile memory for storing encoded multi-state data, the memory including a plurality of units of data access each having a plurality of memory cells; and

read circuitry connectable to the memory to read the data content of said units of data access, whereby during a read process the encoded memory state and the data quality are concurrently determined for each of the memory cells in a given unit of data access.

2. The storage device of claim 1, wherein said data quality comprises information on whether a parameter indicative of the encoded memory state lies within a set of value ranges respectively corresponding to said multi-states.

3. The storage device of claim 2, wherein said parameter corresponds to the threshold value of the read memory cell.

4. The storage device of claim 2, wherein said parameter is cell current.

5. The storage device of claim 2, further comprising:

program circuitry connectable to the memory to write data content to said units of data access;

control circuitry connectable to the program circuitry and read circuitry, whereby in response to the quality of the data determined in a read operation, one or more of the memory cells in a given unit of data access are programmed.

6. The storage device of claim 5, whereby in response to one of said memory cells in a given unit of data access being under-programmed, said under-programmed memory cell is programmed.

7. The storage device of claim 5, further comprising:

erase circuitry connectable to the memory and the control circuitry, whereby in response to one or more of said memory cells in a given unit of data access being over-programmed, the memory cells of the given unit are erased and re-programmed.

8. The storage device of claim 1, wherein quality of data is determined by reading said memory cells with a higher resolution than needed for determining the encoded memory states.

9. A method of operating a storage device comprising a semiconductor memory for storing data, the memory including a plurality of units of data access each comprising a plurality of memory cells, the method comprising:

accessing one of said units of data access; and

concurrently determining the encoded memory state and the data quality for each of the memory cells in said accessed unit of data access.

10. The method of claim 9, further comprising:

performing a scrub operation on said accessed unit based on the data quality of the memory cells in said accessed unit.

11. The method of claim 9, further comprising:

determining whether to perform corrective action on accessed unit based on the data quality of the memory cells in said accessed unit.

12. The method of claim 11, further comprising:

performing corrective action on accessed unit based on the determining.

13. The method of claim 12, further comprising:

incrementing a count when said corrective action is performed; and

comparing said count to a maximum count.

14. The method of claim 13, further comprising:

remapping said accessed unit and subsequently resetting the count when the count equals the maximum count.

15. The method of claim 12, wherein said determining data quality comprises determining a memory cell of the accessed unit is under-programmed and said corrective action comprises programming the under-programmed cell.

16. The method of claim 12, wherein said determining data quality comprises determining a memory cell of the accessed unit is over-programmed and said corrective action comprises erasing and reprogramming the accessed unit.