Methods for predicting board test coverage

• US 6,895,565 B2
• Filed: 10/08/2002
• Issued: 05/17/2005
• Est. Priority Date: 10/08/2002
• Status: Expired due to Fees

• Current Assignee: Agilent Technologies, Inc.
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Parker, Kenneth P
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US10/267,203
• Publication Number:
  US 20040068702A1
• Time in Patent Office: 952 Days
• Field of Search: 716 1- 6, 716/18, 702/179, 702/182, 702/117, 702/118, 714/30, 714/726, 707/3
• US Class Current: 716/106
• CPC Class Codes: G01R 31/2815 Functional tests, e.g. boundary scans, using the normal I/O contacts contacting devices G01R31/2808; testing digital circuits G01R31/317, G06F11/00
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability

Abstract

Disclosed are methods for predicting board test coverage. In one method, board test coverage is predicted by enumerating potentially defective properties for a board design; determining how each of a number of potential test technologies could be applied to the board design; and predicting board test coverage for one or more combinations of the potential test technologies. Board test coverage is predicted for a combination of potential test technologies by, for each potentially defective property enumerated, generating a property score that is indicative of whether a potential test technology could test for the potentially defective property; and combining property scores to predict board test coverage for the combination of potential test technologies.

Claims

1. A method for predicting board test coverage, comprising:

a) enumerating potentially defective properties for a board design;

b) determining how each of a number of potential test technologies could be applied to the board design; and

c) predicting board test coverage for one or more combinations of the potential test technologies by;

i) for each potentially defective property enumerated, generate a property score that is indicative of whether a potential test technology could test for the potentially defective property; and

ii) combining property scores to predict board test coverage for each combination of potential test technologies.

2. The method of claim 1, wherein the board design is embodied in logical but no physical design data.

3. The method of claim 2, wherein the logical design data comprises a netlist and a bill of materials.

4. The method of claim 2, wherein at least some of the potentially defective properties are enumerated in accordance with a PCOLA/SOQ model.

5. The method of claim 2, wherein one potentially defective property is “

short”

; and

wherein potential shorts are enumerated based on logical indications of pin proximity.

6. The method of claim 5, wherein a potential short is enumerated for the pins of a two-terminal device.

7. The method of claim 5, wherein a potential short is enumerated for numerically adjacent pins of a component.

8. The method of claim 1, further comprising displaying test options via a graphical user interface;

wherein the test options are based on the potential test technologies; and

wherein the one or more combinations of potential test technologies for which board test coverage is predicted are determined by a user'"'"'s selection of the test options.

9. A method for predicting board test coverage, comprising:

a) enumerating potentially defective properties for a board design;

b) determining how each of a number of potential test technologies can be applied to the board design, said determination including, enumerating DFT features that enable the potential test technologies to test the board design;

c) predicting board test coverage for one or more combinations of the potential test technologies and enumerated DFT features by;

i) for each potentially defective property enumerated, generating a property score that is indicative of whether a potential test technology could test for the potentially defective property; and

ii) combining property scores to predict board test coverage for each combination of potential test technologies; and

d) for each board test coverage prediction and its corresponding combination of potential test technologies, compiling a list of DFT features on which the board test coverage prediction is based.

10. The method of claim 9, wherein the board design is embodied in logical but no physical design data.

11. The method of claim 10, wherein the logical design data comprises a netlist and a bill of materials.

12. The method of claim 10, wherein at least some of the potentially defective properties are enumerated in accordance with a PCOLA/SOQ model.

13. The method of claim 10, wherein one potentially defective property is “

short”

; and

wherein potential shorts are enumerated based on logical indications of pin proximity.

14. The method of claim 13, wherein a potential short is enumerated for the pins of a two-terminal device.

15. The method of claim 13, wherein a potential short is enumerated for numerically adjacent pins of a component.

16. The method of claim 9, wherein the enumerated DFT features comprise proposed modifications to the board design.

17. The method of claim 9, wherein one of the potential test technologies is Boundary-Scan testing, and one of the DFT features that enables Boundary-Scan testing is inclusion of an IC node in a Boundary-Scan chain.

18. The method of claim 9, wherein one of the potential test technologies is Boundary-Scan testing, and two of the DFT features that enable Boundary-Scan testing are incorporation of Test Access Port (TAP) into the design of an integrated circuit, and probe access to the TAP.

19. The method of claim 9, wherein one of the potential test technologies is TestJet testing, and one of the DFT features that enables TestJet testing is probe access to a component'"'"'s nodes.

20. The method of claim 9, wherein one of the potential test technologies is TestJet testing, and wherein determining how TestJet testing could be applied to the board design comprises determining an integrated circuit'"'"'s package type, and then using the package type to determine whether the integrated circuit is a good candidate for TestJet testing.

21. The method of claim 9, wherein one of the DFT features is probe access to nodes of a component that is deemed to have a higher failure rate than other components.

22. The method of claim 9, wherein one of the DFT features is optical visibility of one or more elements of the board design.

23. The method of claim 9, further comprising:

a) conveying the potential test technologies to a user; and

b) in response to the user selecting a combination of potential test technologies, predicting board test coverage for a combination of;

i) the selected combination of potential test technologies; and

ii) all of the enumerated DFT features corresponding to the selected combination of potential test technologies.

24. The method of claim 9, further comprising:

a) conveying the potential test technologies and enumerated DFT features to a user; and

b) in response to the user selecting a combination of the potential test technologies and enumerated DFT features, predicting board test coverage for the combination.

25. The method of claim 9, further comprising displaying test options via a graphical user interface;

wherein the test options are based on the potential test technologies and/or the enumerated DFT features; and

wherein board test coverage is predicted for one or more user selected test options.

26. The method of claim 9, wherein property scores are combined in accordance with a weighting structure.

27. The method of claim 26, wherein the weighting structure assigns more weight to potentially defective properties that, if manifested in actual defects, are more critical to board operation.

28. The method of claim 26, wherein the weighting structure assigns more weight to potentially defective properties that are more likely to present as actual defects.