Semiconductor process and integrated circuit having dual metal oxide gate dielectric with single metal gate electrode
First Claim
1. A semiconductor fabrication process, comprising:
- forming a first gate dielectric over and in contact with a well region and a second gate dielectric over and in contact with a second well region wherein the compositions of the first and second gate dielectric are different; and
forming a first gate electrode over and in contact with the first gate dielectric and a second gate electrode over and in contact with the second gate dielectric wherein the first and second gate electrodes are equivalent in composition and thickness;
wherein the first gate dielectric includes a second dielectric film overlying a first dielectric film on an upper surface of the first well region and wherein the second gate dielectric includes a third dielectric film overlying the first dielectric film on the upper surface of the second well region.
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Abstract
A semiconductor fabrication process includes forming first and second transistors over first and second well regions, respectively where the first transistor has a first gate dielectric and the second transistor has a second gate dielectric different from the first gate dielectric. The first transistor has a first gate electrode and the second transistor has a second gate electrode. The first and second gate electrodes are the same in composition. The first gate dielectric and the second gate dielectric may both include high-K dielectrics such as Hafnium oxide and Aluminum oxide. The first and second gate electrodes both include a gate electrode layer overlying the respective gate dielectrics. The gate electrode layer is preferably either TaSiN and TaC. The first and second gate electrodes may both include a conductive layer overlying the gate electrode layer. In one such embodiment, the conductive layer may include polysilicon and tungsten.
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Citations
23 Claims
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1. A semiconductor fabrication process, comprising:
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forming a first gate dielectric over and in contact with a well region and a second gate dielectric over and in contact with a second well region wherein the compositions of the first and second gate dielectric are different; and
forming a first gate electrode over and in contact with the first gate dielectric and a second gate electrode over and in contact with the second gate dielectric wherein the first and second gate electrodes are equivalent in composition and thickness;
wherein the first gate dielectric includes a second dielectric film overlying a first dielectric film on an upper surface of the first well region and wherein the second gate dielectric includes a third dielectric film overlying the first dielectric film on the upper surface of the second well region. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A semiconductor process, comprising:
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forming a first transistor over a first well region and a second transistor over a second well region;
the first transistor having a first gate dielectric and the second transistor having a second gate dielectric different in composition from the first gate dielectric;
the first transistor having a first gate electrode and the second transistor having a second gate electrode, wherein the first and second gate electrodes are the same in composition; and
wherein the first gate dielectric and the second gate dielectric are both high-K dielectrics. - View Dependent Claims (9, 10, 11)
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12. An integrated circuit, comprising:
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a first transistor formed overlying a first well region of a semiconductor substrate, wherein the first transistor includes a first gate electrode overlying a first metal-oxide gate dielectric;
a second transistor formed overlying a second wall region of the semiconductor substrate, wherein the second transistor includes a second gate electrode overlying a second metal-oxide gate dielectric;
wherein the first and second gate dielectrics differ in composition and further wherein the first and second gate electrodes are substantially equivalent in composition and thickness. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
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21. A method for forming over a semiconductor substrate a first gate stack in a first gate location for a transistor of a first conductivity type and a second gate stack in a second gate location for a transistor of the second conductivity, comprising:
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forming a first gate dielectric layer over the first gate location and the second gate location, wherein the first gate dielectric layer comprises a first high-k dielectric;
removing the first gate dielectric layer in an area over the second gate location;
forming a second gate dielectric over the first gate location and the second gate location, wherein the second gate dielectric layer comprises a second high-k dielectric different from the first high-k dielectric;
removing the second gate dielectric in an area over the first gate location;
forming a first gate layer over the first gate location and the second gate location;
removing a first portion of the gate layer to leave a second portion of the first gate layer over the first gate location; and
forming a second gate layer over the first gate location and the second gate location;
wherein the removing the first gate dielectric layer occurs before the forming the first gate electrode layer. - View Dependent Claims (22, 23)
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Specification