Test structure and related methods for evaluating stress-induced voiding

• US 6,897,475 B2
• Filed: 04/21/2003
• Issued: 05/24/2005
• Est. Priority Date: 04/21/2003
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Wang, Chien-Jung
• Primary Examiner(s): SARKAR, ASOK K
• Application Number:
  US10/419,617
• Publication Number:
  US 20040207383A1
• Time in Patent Office: 764 Days
• Field of Search: 257/48, 324/71.1, 324/71.5, 438/14, 438/17, 438/18
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2858 Measuring of material aspects, e.g. electro-migration [EM], hot carrier injection
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633

Abstract

This disclosure provides, in one aspect, a test structure formed within a semiconductor wafer. In one embodiment, the test structure comprises a plurality of first level bulk metals having varying sizes, where adjacent ones of the plurality of first level bulk metals are coupled together using vias connected to second level thin conductors located therebetween. In addition, the test structure comprises a plurality of second level bulk metals having varying sizes, where adjacent ones of the plurality of second level bulk metals are coupled together using vias connected to first level thin conductors located therebetween. Furthermore, the test structure includes a first level contact pad coupled to a smallest of the plurality of second level bulk metals, and a second level contact pad coupled to a largest of the plurality of first level bulk metals. In such an embodiment, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals. In other aspects, this disclosure provides a method of manufacturing a test structure within a semiconductor wafer, and a method of evaluating stress-induced voiding of metals within a semiconductor wafer.

Claims

1. A test structure formed within a semiconductor wafer, comprising:

a plurality of first level bulk metal features having varying sizes, wherein adjacent features are coupled to second level thin conductors connected to vias located therebetween;

a plurality of second level bulk metal features having varying sizes, wherein adjacent features are coupled to first level thin conductors connected to vias located therebetween;

a first level contact pad coupled to a smallest of the plurality of second level bulk metal features; and

a second level contact pad coupled to a largest of the plurality of first level bulk metal features, a largest of the second level bulk metals coupled to a smallest of the first level bulk metals.

2. The test structure as recited in claim 1, wherein the plurality of first level bulk metal features having varying sizes comprises a plurality of first level bulk metal features having varying lengths and widths, and wherein the plurality of second level bulk metal features having varying sizes comprises a plurality of second level bulk metal features having varying lengths and widths.

3. The test structure as recited in claim 1, wherein the plurality of first level bulk metal features having varying sizes are arranged in ascending size, and the plurality of second level bulk metal features having varying sizes are arranged in descending size.

4. The test structure as recited in claim 1, wherein each of the first and second level bulk metal features each comprises first and second portions coupled together using a metal trace.

5. The test structure as recited in claim 1, wherein the first level bulk metal features are located on a level over a level of the second level bulk metal features.

6. The test structure as recited in claim 1, wherein a smallest of the second level bulk metal features is located proximate a largest of the first level bulk metal features;

and wherein a largest of the second level bulk metal features is located proximate a smallest of the first level bulk metal features and coupled thereto using a via.

7. The test structure as recited in claim 1, wherein the first level contact pad is coupled to a smallest of the plurality of second level bulk metal features using a via, and the second level contact pad is coupled to a largest of the plurality of first level bulk metal features using a via.