Power device with bi-directional level shift circuit

• US 6,897,492 B2
• Filed: 12/01/2003
• Issued: 05/24/2005
• Est. Priority Date: 02/04/2002
• Status: Expired due to Term

• Current Assignee: Littelfuse Incorporated
• Original Assignee: IXYS Corporation (Littelfuse Incorporated)
• Inventors: Ochi, Sam Seiichiro
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): FORDE, REMMON R
• Application Number:
  US10/726,335
• Publication Number:
  US 20040155692A1
• Time in Patent Office: 540 Days
• Field of Search: 257/107, 257/119, 257/124, 257/130, 257/146, 257/155, 257/157, 257/175, 327/333, 327/112, 327/108, 363/98, 363/97, 363/17, 363/56
• US Class Current: 257/107
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05556 in side view
• CPC Class Codes: H01L 2224/4813 Connecting within a semiconductor or solid-state body, i.e. fly wire, bridge wire
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/48464 the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 23/5228 Resistive arrangements or effects of, or between, wiring layers other resistive arrangements H01L23/647
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 27/0682 comprising combinations of capacitors and resistors
• CPC Class Codes: H01L 27/0805 Capacitors only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 Technical content checked by a classifier
• CPC Class Codes: H01L 2924/1301 Thyristor
• CPC Class Codes: H01L 2924/1305 Bipolar Junction Transistor [BJT]
• CPC Class Codes: H01L 2924/13055 Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/1306 Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H02M 1/08 : Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/088 : for the simultaneous control of series or parallel connected semiconductor devices
• CPC Class Codes: H03K 17/06 : Modifications for ensuring a fully conducting state
• CPC Class Codes: H03K 17/063 : in field-effect transistor switches
• CPC Class Codes: H03K 17/162 : without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6871 : the output circuit comprising more than one controlled field-effect transistor

Abstract

A gate driver includes a control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch. The gate control signal generator is provided proximate a high side of the gate driver. A first sub-circuit has a first signal path and a second signal path that are suitable for transmitting signals. The first and second signal paths are coupled to the first input of the gate control signal generator. The second signal path is configured to provide a signal to the first input with a reduced signal delay. A comparator is configured to receive signals from the high side. The comparator is provided proximate a low side of the gate driver.

Claims

1. A gate driver, comprising:

a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch, the gate control signal generator being provided proximate a high side of the gate driver;

a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals, the first and second signal paths coupled to the first input of the gate control signal generator, the second signal path being configured to provide a signal to the first input with a reduced signal delay; and

a comparator configured to receive signals from the high side, the comparator being provided proximate a low side of the gate driver.

2. The gate driver of claim 1, further comprising:

a second sub-circuit coupled to a second input of the gate control signal generator, wherein the first input of the gate control signal generator receives a signal of first voltage from the first sub-circuit and the second input of the gate control signal generator receives a signal of second voltage from the second sub-circuit, wherein the gate control signal generator outputs a gate control signal according to a voltage difference between the signal of first voltage and the signal of second voltage.

3. The gate driver of claim 2, wherein the second sub-circuit includes a third signal path and a fourth signal path that are suitable for transmitting signals, the third and fourth signal paths coupled to the second input of the gate control signal generator.

4. The gate driver of claim 3, wherein the second signal path and fourth signal path are feed forward connections.

5. The gate driver of claim 1, wherein the first signal path of the first sub-circuit includes a first resistor with a first end configured to receive an input signal and a second end configured to output a signal of first voltage to the first input of the signal generator, and the second signal path including a first capacitor having a first end and a second end, the first end of the first capacitor being electrically coupled to the first end of the first resistor and the second end of the first capacitor being electrically coupled to the second end of the first resistor.

6. The gate driver of claim 5, further comprising:

a second sub-circuit including a third signal path and a fourth signal path that are suitable for transmitting signals, the third and fourth signal paths coupled to a second input of the gate control signal generator.

7. The gate driver of claim 6, wherein the third signal path of the second sub-circuit includes a second resistor with a first end configured to receive an input signal and a second end configured to output a signal of second voltage to the second input of the signal generator, and the fourth signal path including a second capacitor having a first end and a second end, the first end of the second capacitor being electrically coupled to the first end of the second resistor and the second end of the second capacitor being electrically coupled to the second end of the second resistor.

8. The gate driver of claim 1, further comprising:

a second sub-circuit having a third signal path and a fourth signal path that are suitable for transmitting signals, the third and fourth signal paths coupled to the second input of the gate control signal generator, the fourth signal path being configured to provide a signal to the second input with a reduced signal delay;

a third sub-circuit provided in series between the first sub-circuit and the first input of the gate control signal generator, the third sub-circuit including a fifth signal path and a sixth signal path coupled to the first input of the gate control signal generator; and

a fourth sub-circuit provided in series between the second sub-circuit and the second input of the gate control signal generator, the fourth sub-circuit including a seventh signal path and a eighth signal path coupled to the second input of the gate control signal generator.

9. The gate driver of claim 8, wherein the third and fourth sub-circuits provide the gate driver with an increased breakdown voltage.

10. A power module having a high side device and a low side device, comprising:

a gate control signal generator having a first input and configured to output a gate control signal to a power semiconductor switch, the gate control signal generator being provided within the high side device;

a first sub-circuit having a first signal path and a second signal path that are suitable for transmitting signals, the first and second signal paths coupled to the first input of the gate control signal generator, the second signal path being configured to provide a signal to the first input with a reduced signal delay;

a second sub-circuit includes a third signal path and a fourth signal path that are suitable for transmitting signals, the third and fourth signal paths coupled to the second input of the gate control signal generator;

a comparator configured to receive signals from the high side device, the comparator provided at the low side device,

wherein the first input of the gate control signal generator receives a signal of first voltage from the first sub-circuit and the second input of the gate control signal generator receives a signal of second voltage from the second sub-circuit,

wherein the gate control signal generator outputs a gate control signal according to a voltage difference between the signal of first voltage and the signal of second voltage,

wherein the second signal path and fourth signal path are feed forward connections.

11. The module of claim 10, wherein the first signal path of the first sub-circuit includes a first resistor with a first end configured to receive an input signal and a second end configured to output a signal of first voltage to the first input of the signal generator, and the second signal path including a first capacitor having a first end and a second end, the first end of the first capacitor being electrically coupled to the first end of the first resistor and the second end of the first capacitor being electrically coupled to the second end of the first resistor.

12. The module of claim 10, wherein the third signal path of the second sub-circuit includes a second resistor with a first end configured to receive an input signal and a second end configured to output a signal of second voltage to the second input of the signal generator, and the fourth signal path including a second capacitor having a first end and a second end, the first end of the second capacitor being electrically coupled to the first end of the second resistor and the second end of the second capacitor being electrically coupled to the second end of the second resistor.

13. The module of claim 10, further comprising:

a third sub-circuit provided in series between the first sub-circuit and the first input of the gate control signal generator, the third sub-circuit including a fifth signal path and a sixth signal path coupled to the first input of the gate control signal generator; and

a fourth sub-circuit provided in series between the second sub-circuit and the second input of the gate control signal generator, the fourth sub-circuit including a seventh signal path and a eighth signal path coupled to the second input of the gate control signal generator,

wherein the third and fourth sub-circuits provide the gate driver with an increased breakdown voltage.

14. The module of claim 10, further comprising:

a first communication circuit configured to receive a first communication signal;

a second communication circuit configured to receive a second communication signal;

a third communication circuit configured to receive the first communication signal; and

a fourth communication circuit configured to receive the second communication signal,

wherein the first and second communication signals are received at the first input node of the signal control generator to cancel each other, the first and second communication signals are received at the second input node of the signal control generator to cancel each other, and

wherein the first and second communication signals are configured to be input to first and second input of the comparator provided at the low side device, respectively.