Salicided MOS device and one-sided salicided MOS device, and simultaneous fabrication method thereof

• US 6,897,504 B2
• Filed: 03/31/2003
• Issued: 05/24/2005
• Est. Priority Date: 03/31/2003
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yaung, Dun-Nian, Wu, Sou-Kuo, Chen, Ho-Ching
• Primary Examiner(s): Tran, Minhloan
• Assistant Examiner(s): TRAN, TAN N
• Application Number:
  US10/403,474
• Publication Number:
  US 20040188771A1
• Time in Patent Office: 785 Days
• Field of Search: 257/118, 257/229, 257/233, 257/234, 257/257, 257/258, 257/290, 257/291, 257/292, 257/461, 257/462, 257/296, 257/298, 257/300, 257/301, 257/338, 257/357
• US Class Current: 257/296
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/14689 MOS based technologies
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures

Abstract

A method of fabricating a salicided MOS and a one-sided salicided MOS device on a semiconductor substrate. A conformal oxide layer and an organic layer are sequentially formed on first and second MOS devices and the substrate. The first MOS has a first gate structure, a first spacer and first and second doped regions. The second MOS has a second gate structure, a second spacer and third and fourth doped regions. Anisotropic etching is performed to remove part of the organic layer until the oxide layer on the first and the second gate structures is exposed, wherein a remaining organic layer is left above the substrate. The oxide layer on the first and the second gate structures is removed. The remaining organic layer is removed. The oxide layer on the first, second, and third doped regions is removed. Thus, a silicide layer cannot form on the fourth doped region.

Claims

1. A structure of a salicided MOS device and a one-sided salicided MOS device, comprising:

a semiconductor substrate;

a first MOS device and a second MOS device formed on the substrate, wherein the first MOS device comprises a first gate structure formed on the substrate, first and second doped regions formed in the substrate, and the second MOS device comprises a second gate structure formed on the substrate, and third and fourth doped regions formed in the substrate;

a spacer formed on a sidewall of the second gate structure, wherein the spacer is located on part of the fourth doped region;

a conformal insulation layer formed over the fourth doped region and a side of the second gate structure near the fourth doped region, wherein part of the conformal insulation layer overlies the spacer;

a salicided layer formed on the first gate structure, the first doped region, the second doped region, the second gate structure and the third doped region but not the fourth doped region; and

a capacitor electrically coupled to the fourth doped region, wherein part of the conformal insulation layer overlies the capacitor.

2. The structure according to claim 1, wherein the conformal insulation layer is manufactured by the steps of:

forming a conformal previous insulation layer on the first MOS device, the second MOS device and the substrate;

forming a sacrificial layer on the previous insulation layer;

etching back the sacrificial layer until the previous insulation layer on top surfaces of the first and the second gate structures is exposed, wherein a remaining sacrificial layer is left above the substrate;

removing the previous insulation layer on the top surfaces of the first and second gate structures;

removing the remaining sacrificial layer; and

removing the previous insulation layer on the first, second, and third doped regions.

3. The structure according to claim 2, wherein the sacrificial layer is an organic layer.

4. The structure according to claim 1, further comprising a first spacer formed on a first sidewall of the first gate structure, a second spacer formed on a second sidewall of the first gate structure and a third spacer formed on a third sidewall of the second gate structure, wherein the first spacer is located on part of the first doped region, the second spacer is located on part of the second doped region and the third spacer is located on part of the third doped region.

5. The structure according to claim 1, wherein a double insulator comprising the spacer and part of the conformal insulation layer is disposed on the sidewall of the second gate structure.

6. A structure of a one-sided salicided MOS device, suitable for a CMOS image sensor, the CMOS image sensor comprising:

a semiconductor substrate;

a MOS device formed on the substrate, wherein the MOS device has a gate structure on the substrate, first and second doped regions formed in the substrate, a first spacer formed on a first sidewall of the gate structure and a second spacer formed on a second sidewall of the gate structure, wherein the first spacer is located on part of the first doped region and the second spacer is located on part of the second doped region;

a photodiode region formed in the substrate, wherein the photodiode region electrically couples to the second doped region;

a conformal insulation layer formed on the second doped region, the second spacer and the photodiode region; and

a salicided layer formed on the gate structure and the first doped region but not the second doped region and the photodiode region, wherein the conformal insulation layer is lower than a top surface of the salicided layer on the gate structure;

wherein a double insulator, comprising the second spacer and part of the conformal insulation layer, is disposed on the second sidewall of the gate structure, and a single insulator, comprising the first spacer, is disposed on the first sidewall of the gate structure.

7. The structure according to claim 6, wherein the conformal insulation layer is manufactured by the steps of:

forming a conformal previous insulation layer on the MOS device, the photodiode region and the substrate;

forming an organic layer on the previous insulation layer;

performing anisotropic etching to remove part of the organic layer until the previous insulation layer on the top surface of the gate structure is exposed, wherein a remaining organic layer is left above the substrate;

removing the previous insulation layer on the top surface of the gate structure;

removing the remaining organic layer; and

removing the previous insulation layer on the first doped region.

8. The structure according to claim 7, wherein the conformal previous insulation layer is a SiO₂ layer.

9. The structure according to claim 7, wherein the organic layer comprises propylene glycol monomethyl ether.

10. The structure according to claim 6, wherein part of the conformal insulation layer directly overlies a top surface of the photodiode region.

11. The structure according to claim 6, wherein the first and second spacers comprise SiN or SiON.

12. The structure according to claim 6, wherein the conformal insulation layer is a SiO₂ layer.

13. The structure according to claim 6, wherein the salicided layer is a tungsten suicide, titanium silicide, molybdenum silicide, tantalum suicide or cobalt silicide layer.

14. A structure of a salicided MOS device and a one-sided salicided MOS device, comprising:

a semiconductor substrate;

a first MOS device and a second MOS device formed on the substrate, wherein the first MOS device comprises a first gate structure formed on the substrate, first and second doped regions formed in the substrate, and the second MOS device comprises a second gate structure formed on the substrate, and third and fourth doped regions formed in the substrate;

a conformal insulation layer formed over the fourth doped region and a side of the second gate structure near the fourth doped region;

a salicided layer formed on the first gate structure, the first doped region, the second doped region, the second gate structure and the third doped region but not the fourth doped region, wherein the conformal insulation layer is lower than a top surface of salicided layer on the second gate structure; and

a capacitor electrically coupled to the fourth doped region, wherein part of the conformal insulation layer overlies the capacitor.

15. The structure according to claim 14, wherein the conformal insulation layer is manufactured by the steps of:

forming a conformal previous insulation layer on the first MOS device, the second MOS device and the substrate;

forming a sacrificial layer on the previous insulation layer;

etching back the sacrificial layer until the previous insulation layer on top surfaces of the first and the second gate structures is exposed, wherein a remaining sacrificial layer is left above the substrate;

removing the previous insulation layer on the top surfaces of the first and second gate structures;

removing the remaining sacrificial layer; and

removing the previous insulation layer on the first, second, and third doped regions.

16. The structure according to claim 14, further comprising a first spacer formed on a first sidewall of the first gate structure, a second spacer formed on a second sidewall of the first gate structure, a third spacer formed on a third sidewall of the second gate structure and a fourth spacer formed on a fourth sidewall of the second gate structure, wherein the first spacer is located on part of the first doped region, the second spacer is located on part of the second doped region, the third spacer is located on part of the third doped region and the fourth spacer is located on part of the fourth doped region, wherein part of the conformal insulation layer overlies the fourth spacer.

17. The structure according to claim 16, wherein a double insulator comprising the fourth spacer and part of the conformal insulation layer is disposed on the fourth sidewall of the second gate structure.