Capacitor for high performance system-on-chip using post passivation device
First Claim
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1. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:
- a semiconductor substrate having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over said at least one interconnect metal layer wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ
m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ
m PECVD nitride is deposited and wherein said passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
a first layer of conductive material deposited over said passivation layer and within said at least one opening in said passivation layer wherein said first layer of conductive material is connected to said at least one top level metal contact point and wherein said first layer of conductive material forms said bottom plate of said capacitor, a layer of dielectric deposited over the surface of said first layer of conductive material, forming said layer of dielectric interspersed between said top plate and said bottom plate; and
a second layer of conductive material deposited over the surface of said layer of dielectric forming said top plate of said capacitor.
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Abstract
The present invention extends the above referenced continuation-in-part application by in addition creating high quality electrical components, such as inductors, capacitors or resistors, on a layer of passivation or on the surface of a thick layer of polymer. In addition, the process of the invention provides a method for mounting discrete electrical components at a significant distance removed from the underlying silicon surface.
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Citations
21 Claims
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1. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:
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a semiconductor substrate having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over said at least one interconnect metal layer wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ
m of Plasma Enhanced CVD (PECVD) oxide over which a layer within the range of approximately 0.5 to 2.0 μ
m PECVD nitride is deposited and wherein said passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
a first layer of conductive material deposited over said passivation layer and within said at least one opening in said passivation layer wherein said first layer of conductive material is connected to said at least one top level metal contact point and wherein said first layer of conductive material forms said bottom plate of said capacitor, a layer of dielectric deposited over the surface of said first layer of conductive material, forming said layer of dielectric interspersed between said top plate and said bottom plate; and
a second layer of conductive material deposited over the surface of said layer of dielectric forming said top plate of said capacitor. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A capacitor for high performance integrated circuits on the surface of a semiconductor substrate, said capacitor comprising a top plate and a bottom plate and a layer of dielectric interspersed between said top and said bottom plate, comprising:
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a semiconductor substrate having at least one interconnect metal layer over said semiconductor substrate, and a passivation layer over said at least one interconnect metal layer wherein said passivation layer comprises a layer within the range of approximately 0.15 to 2.0 μ
m of silicon oxide underlying a layer within the range of approximately 0.5 to 2.0 μ
m of silicon nitride and wherein said passivation layer comprises at least one passivation opening through which is exposed at least one top level metal contact point;
a polymer insulating, separating layer formed over said passivation layer wherein polymer openings are formed in said polymer insulating, separating layer over each of said passivation openings;
a first layer of conductive material deposited over said passivation layer and within said at least one opening in said polymer layer and in said passivation layer wherein said first layer of conductive material is connected to said at least one top level metal contact point and wherein said first layer of conductive material forms said bottom plate of said capacitor;
a layer of dielectric deposited over the surface of said first layer of conductive material, forming said layer of dielectric interspersed between said top plate and said bottom plate; and
a second layer of conductive material deposited over the surface of said layer of dielectric forming said top plate of said capacitor. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21)
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Specification