Two mask floating gate EEPROM and method of making
First Claim
1. An floating gate transistor, comprising:
- a channel island region;
a source region located adjacent to a first side of the channel island region;
a drain region located adjacent to a second side of the channel island region;
a tunneling dielectric located above the channel island region;
a floating gate having a first, second, third and fourth side surfaces, wherein the floating gate is located above the tunneling dielectric;
a control gate dielectric located above the floating gate;
a control gate located above the control gate dielectric; and
wherein first and second side surfaces of the control gate are aligned to third and fourth side surfaces of the channel island region, and to the third and the fourth side surfaces of the floating gate.
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Abstract
There is provided a floating gate transistor, such as an EEPROM transistor, and method of making the transistor using two masking steps. The method of making a transistor includes patterning a floating gate layer using a first photoresist mask to form a floating gate rail and doping an active area using the floating gate rail as a mask to form source and drain regions in the active area. The method also includes patterning a control gate layer, a control gate dielectric layer, the floating gate rail, a tunnel dielectric layer and the active area using a second photoresist mask to form a control gate, a control gate dielectric, a floating gate, a tunnel dielectric and a channel island region.
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Citations
17 Claims
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1. An floating gate transistor, comprising:
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a channel island region;
a source region located adjacent to a first side of the channel island region;
a drain region located adjacent to a second side of the channel island region;
a tunneling dielectric located above the channel island region;
a floating gate having a first, second, third and fourth side surfaces, wherein the floating gate is located above the tunneling dielectric;
a control gate dielectric located above the floating gate;
a control gate located above the control gate dielectric; and
wherein first and second side surfaces of the control gate are aligned to third and fourth side surfaces of the channel island region, and to the third and the fourth side surfaces of the floating gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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Specification