ESD protection circuit

• US 6,897,536 B2
• Filed: 05/20/2003
• Issued: 05/24/2005
• Est. Priority Date: 06/11/2002
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Suzuki, Teruo, Nomura, Toshio
• Primary Examiner(s): Wilson, Allan R.
• Assistant Examiner(s): Ortiz, Edgardo
• Application Number:
  US10/441,216
• Publication Number:
  US 20030227053A1
• Time in Patent Office: 735 Days
• Field of Search: 257/344, 257/403, 257/404, 257/408, 257/409, 257/548, 257/549
• US Class Current: 257/403
• CPC Class Codes: H01L 27/0277 involving a parasitic bipolar transistor triggered by the local electrical biasing of the layer acting as base of said parasitic bipolar transistor
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

An ESD-protection device includes a gate electrode formed on a substrate; a first diffusion region of a first conductivity type formed in the substrate at a first side of the gate electrode, a second diffusion region of the first conductivity type formed in the substrate at a second side of the gate electrode, and a third diffusion region of a second conductivity type formed in the substrate underneath the second diffusion region in contact with the second diffusion region. Thereby, the impurity concentration level of the third diffusion region is set to be larger than the impurity concentration level of the region of the substrate located at the same depth right underneath the gate electrode.

Claims

1. A semiconductor device, comprising:

a substrate;

a gate electrode formed on said substrate;

a first diffusion region of a first conductivity type formed in said substrate at a first side of said gate electrode;

a second diffusion region of said first conductivity type formed in said substrate at a second side of said gate electrode; and

a third diffusion region of a second conductivity type formed in said substrate underneath said second diffusion region in contact with said second diffusion region,

said third diffusion region containing an impurity element of said second conductivity type with a concentration level larger than a concentration level of an impurity element of said second conductivity type contained in a region right underneath said gate electrode when comparison is made at the same depth in said substrate,

said gate electrode having side wall insulation films at respective sidewall surfaces thereof, said sidewall insulation films extending from a top part of said gate electrode down to a bottom part of said gate electrode at respective sidewall surfaces.

2. The semiconductor device as claimed in claim 1, wherein said substrate is a p-type Si substrate, said first and second diffusion regions have an n-type conductivity, and wherein said third diffusion region has a p-type conductivity.

3. The semiconductor device as claimed in claim 1, wherein said impurity element has a concentration level in said third diffusion region such that the concentration level of said impurity element is larger than a concentration level of an impurity element of said second conductivity type in a region right underneath said gate electrode by a factor of five or more.

4. The semiconductor device as claimed in claim 1, wherein said impurity element has a concentration level in said third diffusion region such that the concentration level of said impurity element is larger than a concentration level of an impurity element of said second conductivity type in a region right underneath said gate electrode by a factor of eight or more.

5. The semiconductor device as claimed in claim 1, wherein a silicide layer is formed on a surface of said second diffusion region with a separation from a sidewall insulation film provided on a sidewall of said gate electrode at said second side.

6. The semiconductor device as claimed in claim 5, wherein an insulation film pattern is provided on said substrate in continuation from said sidewall insulation film up to a region where said silicide layer is formed.

7. The semiconductor device as claimed in claim 6, wherein a drain region of said first conductivity type is formed in said substrate in correspondence to the part on which said silicide layer is formed.

8. The semiconductor device as claimed in claim 5, wherein an insulation film pattern is provided on said substrate at said second side of said gate electrode with a separation from said sidewall insulation film, said semiconductor device further comprising a first silicide region formed on a surface of said second diffusion region at said second side of said insulation film pattern in correspondence to a tip end thereof, a second silicide region formed between said sidewall insulation film and said sidewall insulation pattern, a drain region of said first conductivity type formed in said substrate underneath said first silicide region, and another diffusion region of said first conductivity type formed in said substrate underneath said second silicide region.

9. The semiconductor device as claimed in claim 1, wherein a silicide layer is formed on said gate electrode.

10. A semiconductor device, comprising:

a substrate;

a first gate electrode formed on said substrate;

a first diffusion region of a first conductivity type formed in said substrate at a first side of said gate electrode;

a second diffusion region of said first conductivity type formed in said substrate at a second side of said first gate electrode;

a third diffusion region of a second conductivity type formed in said substrate underneath said second diffusion region in contact with said second diffusion region;

a second gate electrode formed on said substrate at said first side of said gate electrode across said first diffusion region; and

a fourth diffusion region of said first conductivity type formed in said substrate at said first side of said second gate electrode,

said third diffusion region containing an impurity element of said second conductivity type with a concentration larger than a concentration of an impurity element of said second conductivity type in a region right underneath said gate electrode when comparison is made at the same depth in said substrates,

wherein said substrate is a substrate of said second conductivity type, and

wherein said third diffusion layer contacts only with a bottom part of said second diffusion layer.

11. The semiconductor device as claimed in claim 10, wherein an insulation film extends over a surface of said substrate at said second side of said first gate electrode in continuation from a sidewall insulation film covering a sidewall surface of said first gate electrode at said second side, a drain region of said first conductivity type is formed in said substrate in correspondence to a tip end of said insulation film, and a silicide layer is formed on said substrate surface in correspondence to said drain region.

12. A method of fabricating a semiconductor device, comprising the steps of:

forming first and second diffusion regions of a first conductivity type in a substrate by introducing a first impurity element of said first conductivity type into said substrate by an ion implantation process while using a gate electrode pattern as a mask, such that said first and second diffusion regions are formed respectively at a first side and a second side of said gate electrode;

forming third and fourth diffusion regions of a second conductivity type in said substrate respectively underneath said first and second diffusion regions by introducing a second impurity element of said first conductivity type and a third impurity element of said second conductivity type into said substrate by an ion implantation process while using said gate electrode pattern and sidewall insulation films formed at both lateral sidewall surfaces of said gate electrode as a mask; and

forming a silicide layer on a surface of said first and second diffusion regions,

said step of forming said third and fourth diffusion regions being conducted by covering said gate electrode pattern by a resist pattern.

13. A fabrication process of a semiconductor device, comprising the steps of:

forming first and second diffusion regions of a first conductivity type by introducing a first impurity element of said first conductivity type into a substrate by an ion implantation process while using a gate electrode pattern as a mask, such that said first and second diffusion regions are formed respectively at a first side and a second side of said gate electrode;

forming third and fourth diffusion regions of said first conductivity type respectively underneath said first and second diffusion regions by introducing a second impurity element of said first conductivity type and a third impurity element of a second conductivity type into said substrate by an ion implantation process while using said gate electrode pattern and sidewall insulation films formed at both lateral sidewall surfaces of said gate electrode as a mask;

forming an insulation film pattern on said substrate at said second side of said gate electrode such that said insulation film pattern extends along a surface of said substrate in the direction of said second side; and

forming a silicide layer on said surface of said substrate at a tip end part of said insulation film pattern while using said insulation film pattern as a mask,

wherein said substrate is a substrate of said second conductivity type, and

wherein said third diffusion layer contacts only with a bottom part of said second diffusion layer.

14. The method of fabricating a semiconductor device, comprising the steps of:

forming first and second diffusion regions of a first conductivity type by introducing a first impurity element of said first conductivity type into a substrate by an ion implantation process while using a gate electrode pattern as a mask, such that said first and second diffusion regions are formed respectively at a first side and a second side of said gate electrode;

forming a third diffusion region of a second conductivity type in said substrate in a region in which said second diffusion region is formed by introducing an impurity element of said second conductivity type, such that said third diffusion region is located at a depth deeper than a depth of said second diffusion region;

forming a fourth diffusion region in said substrate in said region in which said second diffusion region is formed by introducing an impurity element of said first conductivity type, such that said fourth diffusion region is located at a depth shallower than a depth of said second diffusion region;

forming an insulation film pattern on said substrate at said second side of said gate electrode such that said insulation film pattern extends in the direction of said second side along a surface of said substrate; and

forming a silicide layer on said surface of said substrate at a tip end part of said insulation film pattern while using said insulation film pattern as a mask,

wherein said substrate is a substrate of said second conductivity type, and

wherein said third diffusion layer contacts only with a bottom part of said second diffusion layer.

15. The method as claimed in claim 14, further comprising the step, after said step of forming said insulation film pattern, of forming a diffusion region of said first conductivity type as a drain region by introducing an impurity element of said first conductivity type into said substrate.

16. An ESD-protection device, comprising:

a substrate;

a semiconductor device formed on said substrate, said semiconductor device comprising;

a gate electrode formed on said substrate;

a first diffusion region of a first conductivity type formed in said substrate at a first side of said gate electrode;

a second diffusion region of said first conductivity type formed in said substrate at a second side of said gate electrode; and

a third diffusion region of a second conductivity type formed in said substrate underneath said second diffusion region in contact with said second diffusion region, said third diffusion region containing an impurity element of said second conductivity type with a concentration level larger than a concentration level of an impurity element of said second conductivity type contained in a region right underneath said gate electrode when comparison is made at the same depth in said substrate; and

an electrode pad provided on said substrate in electrical connection with said second diffusion region,

said gate electrode pattern and said first diffusion region being connected to a power supply line,

wherein said substrate is a substrate of said second conductivity type, and

wherein said third diffusion layer contacts only with a bottom part of said second diffusion layer.