Apparatus to prevent damage to probe card

• US 6,897,672 B2
• Filed: 12/20/2002
• Issued: 05/24/2005
• Est. Priority Date: 06/25/2001
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Byrd, Phillip E.
• Primary Examiner(s): Zarneke, David A.
• Assistant Examiner(s): Nguyen, Trung Q.
• Application Number:
  US10/327,469
• Publication Number:
  US 20030128041A1
• Time in Patent Office: 886 Days
• Field of Search: 324/158.1, 324/754, 324/765, 324/763, 324/764, 324/759, 324/750, 324/537, 714/726
• US Class Current: 324/750.05
• CPC Class Codes: G01R 1/06766 Input circuits therefor
• CPC Class Codes: G01R 1/07371 using an intermediate card or back card with apertures through which the probes pass
• CPC Class Codes: G01R 1/36 Overload-protection arrangements or circuits for electric measuring instruments
• CPC Class Codes: G01R 3/00 Apparatus or processes specially adapted for the manufacture or maintenance of measuring instruments , e.g. of probe tips
• CPC Class Codes: G01R 31/2886 Features relating to contacting the IC under test, e.g. probe heads; chucks G01R31/2865 takes precedence, test connections, e.g. test sockets, or probes per se, G01R1/04 or G01R1/06
• CPC Class Codes: H05K 1/0293 Individual printed conductors which are adapted for modification, e.g. fusable or breakable conductors, printed switches
• CPC Class Codes: H05K 1/09 Use of materials for the conductive, e.g. metallic pattern
• CPC Class Codes: H05K 1/167 incorporating printed resistors
• CPC Class Codes: H05K 2201/068 wherein the coefficient of thermal expansion is important
• CPC Class Codes: H05K 2201/10053 Switch
• CPC Class Codes: H05K 2201/10181 Fuse
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49005 Acoustic transducer
• CPC Class Codes: Y10T 29/49107 Fuse making
• CPC Class Codes: Y10T 29/49117 Conductor or circuit manufacturing
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49139 by inserting component lead or terminal into base aperture
• CPC Class Codes: Y10T 29/49147 Assembling terminal to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49204 : Contact or terminal manufacturing

Abstract

Probe cards are configured with protective circuitry suitable for use in electrical testing of semiconductor dice without damage to the probe cards. Protective fuses are provided in electrical communication with conductive traces and probe elements (e.g., probe needles) of a probe card. The fuses may be active or passive fuses and are preferably self-resetting, repairable, and/or replaceable. Typically, the fuses will be interposed in, or located adjacent to, conductive traces residing over a surface of the probe card. Methods of fabricating a probe card are provided, as well as various probe card configurations. A semiconductor die testing system using the probe card is also provided.

Claims

1. A semiconductor die testing system comprising:

a probe card for use as an interface for a testing computer for testing at least one semiconductor die having at least one bond pad including;

a substrate having a first surface and a second surface forming a surface of the probe card during the testing of at least one semiconductor die using a testing computer;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface, at least one conductive trace for carrying current during the testing of at least one semiconductor die using a testing computer;

a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements for contacting the at least one bond pad of the semiconductor die during testing; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface, the plurality of fuses in electrical communication with the plurality of conductive traces for conducting current below a predetermined maximum level and for preventing conducting current when the current is above a predetermined maximum level during the testing of the semiconductor die; and

semiconductor device testing apparatus linkable with the probe card, the semiconductor device testing apparatus configured for sending test signals through the probe card.

2. The semiconductor die testing system of claim 1, wherein the probe card is configured as a needle-type probe card.

3. The semiconductor die testing system of claim 1, wherein the probe card is configured as a membrane-type probe card.

4. The semiconductor die testing system of claim 1, wherein the probe card is configured as a probe card selected from the group consisting of vertical contact probe cards, cantilever-type probe cards, and probe cards for wafer level bum-in.

5. The semiconductor die testing system of claim 1, wherein the probe card is configured for the testing of a plurality of semiconductor dice at once.

6. A semiconductor die testing system comprising:

a probe card including;

a substrate having a first surface and a second surface;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface;

a plurality of probe elements in electrical communication with the plurality of conductive traces;

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface, the plurality of fuses in electrical communication with the plurality of conductive traces; and

a pogo pin interfacing the probe card and a semiconductor device testing apparatus, and wherein a portion of the pogo pin is configured as a protective fuse in electrical communication with the probe card; and

semiconductor device testing apparatus linkable with the probe card, the semiconductor device testing apparatus configured for sending test signals through the probe card.

7. A testing system comprising:

a probe card used as an interface for a semiconductor device testing apparatus for testing at least one semiconductor die having at least one bond pad including;

a substrate having a first surface and a second surface forming surfaces of the probe card during testing of at least one semiconductor die using a semiconductor device testing apparatus;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface, at least one conductive trace for carrying current during the testing of at least one semiconductor die using a semiconductor device testing apparatus;

a plurality of probe elements in electrical communication with the plurality of conductive traces, at least one probe element of the plurality of probe elements for contacting the at least one bond pad of the semiconductor die during testing; and

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface, the plurality of fuses in electrical communication with the plurality of conductive traces for conducting current below a predetermined maximum level and for preventing conducting current when the current is above a predetermined maximum level during the testing of a semiconductor die; and

semiconductor device testing apparatus linkable with the probe card, the semiconductor device testing apparatus configured for sending test signals through the probe card.

8. The testing system of claim 7, wherein the probe card is configured as a needle-type probe card.

9. The testing system of claim 7, wherein the probe card is configured as a membrane-type probe card.

10. The testing system of claim 7, wherein the probe card is configured as a probe card selected from the group consisting of vertical contact probe cards, cantilever-type probe cards, and probe cards for wafer level burn-in.

11. The testing system of claim 7, wherein the probe card is configured for the testing of a plurality of semiconductor dice at once.

12. A testing system comprising:

a probe card including;

a substrate having a first surface and a second surface;

a plurality of conductive traces disposed adjacent at least one of the first surface and the second surface;

a plurality of probe elements in electrical communication with the plurality of conductive traces;

a plurality of fuses disposed adjacent the at least one of the first surface and the second surface, the plurality of fuses in electrical communication with the plurality of conductive traces; and

a pogo pin interfacing the probe card and a semiconductor device testing apparatus, and wherein a portion of the pogo pin is configured as a protective fuse in electrical communication with the probe card; and

semiconductor device testing apparatus linkable with the probe card, the semiconductor device testing apparatus configured for sending test signals through the probe card.