Phase shifting and PWM driving circuits and methods
First Claim
1. An inverter controller comprising a drive circuit that generates a plurality of switch drive signals by reversing the command level of an error signal, said drive circuit comprising:
- an oscillator circuit generating a first and second complimentary clock pulses and a sawtooth signal;
a break-before-make circuit receiving said first and second complimentary clock pulses and generating a first and second switch drive signals;
a first comparator comparing an error signal and said sawtooth signal, and a second comparator comparing a compliment of said error signal and said sawtooth signal; and
a phase generating circuit receiving the outputs of said first and second comparators and generating a third and fourth drive switch drive signals, said third and fourth switch drive signals having a phase with respect to said first and second switch drive signals, respectively, said phase determined by said error signal.
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Abstract
The present invention provides an inverter controller comprising a drive circuit that generates a plurality of switch drive signals for inverter applications. In some exemplary embodiments, the drive circuit operates by reversing the command level of an error signal. In other embodiments, the drive circuit operates by using a half period of a sawtooth signal. In still other embodiments, the drive circuit operates by using a double period opposite shifting pulses method. The present invention also provides a PWM signal generator circuit that generates periodic PWM switch drive signals symmetrical to the minimum or maximum of a sawtooth waveform.
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Citations
4 Claims
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1. An inverter controller comprising a drive circuit that generates a plurality of switch drive signals by reversing the command level of an error signal, said drive circuit comprising:
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an oscillator circuit generating a first and second complimentary clock pulses and a sawtooth signal;
a break-before-make circuit receiving said first and second complimentary clock pulses and generating a first and second switch drive signals;
a first comparator comparing an error signal and said sawtooth signal, and a second comparator comparing a compliment of said error signal and said sawtooth signal; and
a phase generating circuit receiving the outputs of said first and second comparators and generating a third and fourth drive switch drive signals, said third and fourth switch drive signals having a phase with respect to said first and second switch drive signals, respectively, said phase determined by said error signal. - View Dependent Claims (2, 3, 4)
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Specification
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- Resources
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Current AssigneeO2 Micro International Limited (O2 Micro Incorporated)
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Original AssigneeO2 Micro International Limited (O2 Micro Incorporated)
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InventorsGheorghiu, Virgil Ioan, Liu, Da
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Primary Examiner(s)Lam, Tuan T.
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Assistant Examiner(s)Nguyen, Hiep
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Application NumberUS10/448,496Time in Patent Office725 DaysField of Search327/172, 327/175, 327/254, 327/255, 327/256, 327/257, 327/258, 327/259, 327/231, 327/232, 327/233, 327/236US Class Current327/231CPC Class CodesH02M 3/158 including plural semiconduc...H02M 3/33571 Half-bridge at primary side...H02M 3/33573 Full-bridge at primary side...
