Method and apparatus for run length limited TMDS-like encoding of data

• US 6,897,793 B1
• Filed: 04/29/2004
• Issued: 05/24/2005
• Est. Priority Date: 04/29/2004
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Choi, Hoon, Kim, Min-Kyu, Shim, Daeyun, Kim, Gyudong
• Primary Examiner(s): Jeanglaude, Jean Bruner
• Application Number:
  US10/835,301
• Time in Patent Office: 390 Days
• Field of Search: 341/59, 341/67, 341/50, 375/242, 714/782, 714/756, 714/758, 714/752, 360/40
• US Class Current: 341/59
• CPC Class Codes: H03M 5/145 Conversion to or from block codes or representations thereof

Abstract

A serial data transmission system in which a transmitter encodes data in accordance with a TMDS-like encoding algorithm and transmits the TMDS-like encoded data over a serial link to a receiver. The encoded data are transmitted as a run length limited (“RLL”) code word sequence, including transition-minimized code words. In some embodiments, the RLL code word sequence includes only Min words, including both DC balancing Min words and DC unbalancing Min words. In other embodiments, the RLL code word sequence includes both transition-maximized code words and transition-minimized code words. Other aspects of the invention are circuitry and methods for TMDS-like encoding of data for transmission as an RLL code word sequence.

Claims

1. An encoder configured to receive a data word sequence of N-bit data words and to generate a code word sequence of M-bit code words by encoding the data words, where M>

N, said encoder including;

candidate code word generation circuitry configured to generate an M-bit, transition-minimized, candidate code word in response to each N-bit data word of the data word sequence; and

logic circuitry coupled to the candidate code word generation circuitry and configured to generate the code word sequence, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of a predetermined value, where the current candidate code word is one said candidate code word, to include the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and to include an M-bit substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, whereby the code word sequence is a run length limited code word sequence including no run of length in excess of the predetermined value.

2. The encoder of claim 1, wherein the candidate code word generation circuitry is configured to generate a candidate code word and at least one M-bit substitute code word that corresponds to the candidate code word in response to each data word of the data word sequence and to assert the most recently generated candidate code word and each substitute code word corresponding thereto to the logic circuitry, the current candidate code word is said most recently generated candidate code word, and

the logic circuitry is configured to include in the code word sequence a substitute code word that corresponds to the most recently generated candidate code word, rather than the most recently generated candidate code word, in response to determining that the most recently generated candidate code word concatenated with the at least one previously generated bit of the code word sequence includes said run of length in excess of the predetermined value.

3. The encoder of claim 1, wherein each said substitute code word is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.

4. The encoder of claim 1, wherein the candidate code word generation circuitry is configured to generate each candidate code word in accordance with a DC balancing algorithm such that each candidate code word is a DC balancing word and to generate one candidate code word and a corresponding DC unbalancing word in response to each data word of the data word sequence, each said DC unbalancing word is an M-bit, transition-minimized word including a bit sequence which is the complement of a corresponding bit sequence in the DC balancing word to which the DC unbalancing word corresponds, and each said substitute code word is one said DC unbalancing word.

5. The encoder of claim 1, wherein the code word sequence consists of transition-minimized code words and transition-maximized code words, each of the transition-minimized code words having less than a predetermined number of transitions between consecutive bits thereof, and each the transition-maximized code words having more than the predetermined number of transitions between consecutive bits thereof.

6. The encoder of claim 1, wherein each of the code words of the code word sequence is a transition-minimized code word having less than a predetermined number of transitions between consecutive bits thereof.

7. The encoder of claim 1, wherein the logic circuitry is configured to determine whether the current candidate code word concatenated with the X trailing bits of the code word sequence includes a run of length in excess of the predetermined value, where X is an integer.

8. The encoder of claim 1, wherein said predetermined value is an integer X, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence and whether the X trailing bits of the code word sequence are identical.

9. The encoder of claim 8, wherein the X trailing bits of the code word sequence are the X most significant bits of one of the code words of said code word sequence, and the leading bit of each candidate code word is the candidate code word'"'"'s least significant bit.

10. The encoder of claim 1, wherein said predetermined value is an integer X+Y, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence, whether the X trailing bits of the code word sequence are identical and whether the Y leading bits of the current candidate code word are identical.

11. The encoder of claim 1, wherein the candidate code word generation circuitry includes at least one look-up table.

12. The encoder of claim 1, wherein the candidate code word generation circuitry is code word generation logic.

13. A transmitter configured to receive a data word sequence of N-bit data words, to generate a code word sequence of M-bit code words by encoding the data words, where M>

N, and to transmit a signal indicative of the code word sequence over a serial link, said transmitter including;

candidate code word generation circuitry configured to generate an M-bit, transition-minimized, candidate code word in response to each N-bit data word of the data word sequence; and

logic circuitry coupled to the candidate code word generation circuitry and configured to generate the code word sequence, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of a predetermined value, where the current candidate code word is one said candidate code word, to include the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and to include an M-bit substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, whereby the code word sequence is a run length limited code word sequence including no run of length in excess of the predetermined value.

14. The transmitter of claim 13, wherein the candidate code word generation circuitry is configured to generate a candidate code word and at least one M-bit substitute code word that corresponds to the candidate code word in response to each data word of the data word sequence and to assert the most recently generated candidate code word and each substitute code word corresponding thereto to the logic circuitry, the current candidate code word is said most recently generated candidate code word, and

the logic circuitry is configured to include in the code word sequence a substitute code word that corresponds to the most recently generated candidate code word rather than the most recently generated candidate code word in response to determining that the most recently generated candidate code word concatenated with said at least one previously generated bit of the code word sequence includes said run of length in excess of the predetermined value.

15. The transmitter of claim 13, wherein each said substitute code word is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.

16. The transmitter of claim 13, wherein the candidate code word generation circuitry is configured to generate each candidate code word in accordance with a DC balancing algorithm such that each candidate code word is a DC balancing word and to generate one candidate code word and a corresponding DC unbalancing word in response to each data word of the data word sequence, each said DC unbalancing word is an M-bit, transition-minimized word including a bit sequence which is the complement of a corresponding bit sequence in the DC balancing word to which the DC unbalancing word corresponds, and each said substitute code word is one said DC unbalancing word.

17. The transmitter of claim 13, wherein the code word sequence consists of transition-minimized code words and transition-maximized code words, each of the transition-minimized code words having less than a predetermined number of transitions between consecutive bits thereof, and each the transition-maximized code words having more than the predetermined number of transitions between consecutive bits thereof.

18. The transmitter of claim 13, wherein each of the code words of the code word sequence is a transition-minimized code word having less than a predetermined number of transitions between consecutive bits thereof.

19. The transmitter of claim 13, wherein the logic circuitry is configured to determine whether the current candidate code word concatenated with the X trailing bits of the code word sequence includes a run of length in excess of the predetermined value, where X is an integer.

20. The transmitter of claim 13, wherein said predetermined value is an integer X, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence and whether the X trailing bits of the code word sequence are identical.

21. The transmitter of claim 20, wherein the X trailing bits of the code word sequence are the X most significant bits of one of the code words of said code word sequence, and the leading bit of each candidate code word is the candidate code word'"'"'s least significant bit.

22. The transmitter of claim 13, wherein said predetermined value is an integer X+Y, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence, whether the X trailing bits of the code word sequence are identical and whether the Y leading bits of the current candidate code word are identical.

23. The transmitter of claim 13, wherein the candidate code word generation circuitry includes at least one look-up table.

24. The transmitter of claim 13, wherein the candidate code word generation circuitry is code word generation logic.

25. A serial data transmission system, including:

a transmitter configured to receive a data word sequence of N-bit data words and to generate a code word sequence of M-bit code words by encoding the data words, where M>

N;

a receiver coupled to receive a signal indicative of the code word sequence and configured to recover the data words from the signal including by decoding the code word sequence; and

a serial link between the transmitter and the receiver, wherein the transmitter is configured to generate the signal and to transmit said signal over the link to the receiver, said transmitter including;

candidate code word generation circuitry configured to generate an M-bit, transition-minimized, candidate code word in response to each N-bit data word of the data word sequence; and

logic circuitry coupled to the candidate code word generation circuitry and configured to generate the code word sequence, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of a predetermined value, where the current candidate code word is one said candidate code word, to include the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and to include an M-bit substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, whereby the code word sequence is a run length limited code word sequence including no run of length in excess of the predetermined value.

26. The system of claim 25, wherein the candidate code word generation circuitry is configured to generate a candidate code word and at least one M-bit substitute code word that corresponds to the candidate code word in response to each data word of the data word sequence and to assert the most recently generated candidate code word and each substitute code word corresponding thereto to the logic circuitry, the current candidate code word is said most recently generated candidate code word, and

the logic circuitry is configured to include in the code word sequence a substitute code word that corresponds to the most recently generated candidate code word rather than the most recently generated candidate code word in response to determining that the most recently generated candidate code word concatenated with said at least one previously generated bit of the code word sequence includes said run of length in excess of the predetermined value.

27. The system of claim 25, wherein each said substitute code word is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.

28. The system of claim 25, wherein the candidate code word generation circuitry is configured to generate each candidate code word in accordance with a DC balancing algorithm such that each candidate code word is a DC balancing word and to generate one candidate code word and a corresponding DC unbalancing word in response to each data word of the data word sequence, each said DC unbalancing word is an M-bit, transition-minimized word including a bit sequence which is the complement of a corresponding bit sequence in the DC balancing word to which the DC unbalancing word corresponds, and each said substitute code word is one said DC unbalancing word.

29. The system of claim 25, wherein the code word sequence consists of transition-minimized code words and transition-maximized code words, each of the transition-minimized code words having less than a predetermined number of transitions between consecutive bits thereof, and each the transition-maximized code words having more than the predetermined number of transitions between consecutive bits thereof.

30. The system of claim 25, wherein each of the code words of the code word sequence is a transition-minimized code word having less than a predetermined number of transitions between consecutive bits thereof.

31. The system of claim 25, wherein the logic circuitry is configured to determine whether the current candidate code word concatenated with the X trailing bits of the code word sequence includes a run of length in excess of the predetermined value, where X is an integer.

32. The system of claim 25, wherein said predetermined value is an integer X, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence and whether the X trailing bits of the code word sequence are identical.

33. The system of claim 25, wherein said predetermined value is an integer X+Y, and the logic circuitry is configured to determine whether the leading bit of the current candidate code word matches the trailing bit of the code word sequence, whether the X trailing bits of the code word sequence are identical and whether the Y leading bits of the current candidate code word are identical.

34. The system of claim 25, wherein the candidate code word generation circuitry includes at least one look-up table.

35. The system of claim 25, wherein the candidate code word generation circuitry is code word generation logic.

36. A serial data transmission system, including:

a serial link;

a receiver coupled to the link and configured to receive a signal that has propagated over the link, wherein the signal is indicative of encoded data that have been generated by encoding data in accordance with a TMDS-like encoding algorithm having an inverse, and the receiver is configured to recover the data from the signal including by decoding the encoded data in accordance with the algorithm'"'"'s inverse; and

a transmitter coupled to the link and configured to generate a code word sequence of M-bit code words in response to a data word sequence of N-bit data words by encoding the data words in accordance with a modified version of the algorithm, where M>

N, including by generating M-bit candidate code words in response to the data words in accordance with the algorithm, and substituting M-bit substitute code words for selected ones of the candidate words in accordance with the modified version of the algorithm such that the code word sequence is a run length limited code word sequence including no run of length in excess of a predetermined value,

wherein the transmitter is configured to generate a run length limited signal indicative of the code word sequence and to transmit the run length limited signal over the link to the receiver, wherein the modified version of the algorithm is such that the receiver is capable of recovering the data words from the run length limited signal including by decoding the code word sequence in accordance with the inverse of the algorithm.

37. The system of claim 36, wherein each of the candidate code words is an M-bit, transition-minimized code word, and wherein the transmitter includes:

logic circuitry configured to generate the code word sequence, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, where the current candidate code word is one of the candidate code words, to include the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and to include one of the substitute code words that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value.

38. The system of claim 36, wherein the transmitter also includes:

code word generation circuitry configured to generate a candidate code word and at least one substitute code word that corresponds to the candidate code word in response to each data word of the data word sequence and to assert the most recently generated candidate code word and each substitute code word corresponding thereto to the logic circuitry, the current candidate code word is said most recently generated candidate code word, and

wherein the logic circuitry is configured to include in the code word sequence a substitute code word that corresponds to the most recently generated candidate code word rather than the most recently generated candidate code word in response to determining that the most recently generated candidate code word concatenated with said at least one previously generated bit of the code word sequence includes said run of length in excess of the predetermined value.

39. The system of claim 38, wherein the code word generation circuitry is configured to generate each candidate code word in accordance with a DC balancing algorithm such that each candidate code word is a DC balancing word and to generate one candidate code word and a corresponding DC unbalancing word in response to each data word of the data word sequence, each said DC unbalancing word is an M-bit, transition-minimized word including a bit sequence which is the complement of a corresponding bit sequence in the DC balancing word to which the DC unbalancing word corresponds, and each said substitute code word is one said DC unbalancing word.

40. The system of claim 38, wherein each said substitute code word is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.

41. The system of claim 36, wherein the code word sequence consists of transition-minimized code words and transition-maximized code words, each of the transition-minimized code words having less than a predetermined number of transitions between consecutive bits thereof, and each the transition-maximized code words having more than the predetermined number of transitions between consecutive bits thereof.

42. The system of claim 36, wherein each of the code words of the code word sequence is a transition-minimized code word having less than a predetermined number of transitions between consecutive bits thereof.

43. A TMDS-like encoding method for generating a code word sequence of M-bit code words by encoding N-bit data words of a data word sequence, where M>

N, said method including the steps of;

(a) generating a sequence of candidate code words, including by generating an M-bit, transition-minimized candidate code word in response to each N-bit data word of the data word sequence; and

(b) generating the code word sequence using the candidate code words, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of a predetermined value, including the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and including an M-bit substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, whereby the code word sequence is a run length limited code word sequence including no run of length in excess of the predetermined value.

44. The method of claim 43, wherein step (a) includes the step of:

in response to each data word of the data word sequence, generating at least one M-bit substitute code word that corresponds to the candidate code word generated in response to said data word.

45. The method of claim 44, wherein each candidate code word is a DC balancing word, and each substitute code word that corresponds to one said candidate code word is a transition-minimized DC unbalancing word including a bit sequence which is the complement of a corresponding bit sequence in the candidate code word to which the DC unbalancing word corresponds.

46. The method of claim 43, wherein each said substitute code word is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.

47. The method of claim 43, wherein the current candidate code word is the most recently generated candidate code word.

48. A method for data transmission over a serial link to a receiver, wherein the receiver is configured to recover data from a signal that has propagated over the link to said receiver, the signal is indicative of encoded data that have been generated by encoding data in accordance with a TMDS-like encoding algorithm having an inverse, and the receiver is configured to recover the data from the signal including by decoding the encoded data in accordance with the algorithm'"'"'s inverse, said method including the steps of:

(a) generating a code word sequence of M-bit code words by encoding N-bit data words of a data word sequence in accordance with a modified version of the algorithm, where M>

N, including by generating M-bit, transition-minimized candidate code words in response to the data words in accordance with the algorithm and substituting M-bit substitute code words for selected ones of the candidate code words in accordance with the modified version of the algorithm such that the code word sequence is a run length limited code word sequence including no run of length in excess of a predetermined value; and

(b) transmitting a run length limited signal indicative of the code word sequence over the link to the receiver, wherein the modified version of the algorithm is such that the receiver is capable of recovering the data words from the run length limited signal including by decoding the code word sequence in accordance with the inverse of the algorithm.

49. The method of claim 48, wherein step (a) includes the step of:

in response to each data word of the data word sequence, generating at least one M-bit substitute code word that corresponds to the candidate code word generated in response to said data word.

50. The method of claim 48, wherein each candidate code word is a DC balancing word, and each substitute code word that corresponds to one said candidate code word is a transition-minimized DC unbalancing word including a bit sequence which is the complement of a corresponding bit sequence in the candidate code word to which the DC unbalancing word corresponds.

51. The method of claim 48, wherein step (a) includes the steps of:

generating the code word sequence using the candidate code words, including by determining whether a current candidate code word concatenated with at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value, including the current candidate code word in the code word sequence in response to determining that the current candidate code word concatenated with said at least one previously generated bit of the code word sequence includes no run of length in excess of the predetermined value, and including one said substitute code word that corresponds to the current candidate code word in the code word sequence rather than the current candidate code word in response to determining that the current candidate code word concatenated with the at least one previously generated bit of the code word sequence includes a run of length in excess of the predetermined value.

52. The method of claim 51, wherein the current candidate code word is the most recently generated candidate code word.

53. The method of claim 48, wherein each of the substitute code words is a transition-maximized code word having more than a predetermined number of transitions between consecutive bits thereof, and each said candidate code word is a transition-minimized code word having less than the predetermined number of transitions between consecutive bits thereof.