Microcontroller with programmable logic on a single chip

• US 6,898,101 B1
• Filed: 12/16/1997
• Issued: 05/24/2005
• Est. Priority Date: 12/16/1997
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Mann, Eric N.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US08/991,232
• Time in Patent Office: 2,716 Days
• Field of Search: 365/52, 365/63, 365/189.01, 365/189.05, 365/154, 365/230.02, 326/37, 326/41, 326/38, 326/39
• US Class Current: 365/51
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture

Abstract

A programmable logic device, a memory device and a microcontroller manufactured on a single integrated circuit chip. In one example, the programmable logic device may comprise one or more macrocells each comprising an input/output macrocell or a buried macrocell. In another example, the programmable logic device may be a complex programmable logic device (CPLD) or a programmable logic array (PLA).

Claims

1. A circuit comprising:

a programmable logic circuit;

a microcontroller connected to said programmable logic device through a first bus; and

a memory array connected to said microcontroller through a second bus, wherein said microcontroller, said programmable device, said memory array, said first bus and said second bus are fabricated as a single integrated circuit chip.

2. The circuit according to claim 1, wherein said programmable logic circuit comprises one or more macrocells.

3. The circuit according to claim 2, wherein one or more of said macrocells comprises an input/output macrocell.

4. The circuit according to claim 3, wherein said one or more input/output macrocells comprise a memory section that may be configured as a memory element selected from the group consisting of:

a D-flip-flop, a T-flip-flop, a latch and a buffer.

5. The circuit according to claim 3, wherein said one or more input/output macrocells comprises an input/output pin.

6. The circuit according to claim 4, wherein said memory section is configured in response to one or more configuration bits from said memory array.

7. The circuit according to claim 2, wherein one or more of said macrocells comprises a buried macrocell.

8. The circuit according to claim 7, wherein said one or more buried macrocell comprise a memory section that may be configured as a memory element selected from the group consisting of:

a D-flip-flop, a T-flip-flop, a latch and a buffer.

9. The circuit according to claim 2, wherein one or more of said macrocells comprises a multiplexor.

10. The circuit according to claim 9, wherein said multiplexor comprises one or more product term inputs and one or more control signals.

11. The circuit according to claim 1, wherein said memory array comprises a read only memory.

12. The circuit according to claim 1, wherein said memory array comprises an erasable read only memory.

13. The circuit according to claim 1, wherein said memory array comprises an erasable and programmable memory.

14. The circuit according to claim 1 wherein said programmable logic circuit is selected from the group consisting of:

a complex programmable logic device (CPLD) and a programmable logic array (PLA).

15. The circuit according to claim 1, wherein said memory array is connected only to said microcontroller.

16. The circuit according to claim 1, wherein said programmable logic circuit comprises a programmable interconnect matrix that connects one or more of an address, a control and a data out signal to said microcontroller.

17. The circuit according to claim 16, wherein said programmable interconnect matrix provides at least one of a wired AND or a wired OR.

18. The circuit according to claim 16, wherein said programmable interconnect matrix is configured to receive one or more external inputs.

19. A circuit comprising:

a programmable logic circuit;

means for processing information connected to said programmable logic circuit through a first bus; and

a memory array connected to said processing means through a second bus, wherein said programmable logic circuit, said memory array, said first bus, said second bus, and said processing means are fabricated on a single integrated circuit chip.

20. The circuit according to claim 19, wherein said programmable logic circuit is selected from the group consisting of:

a complex programmable logic device (CPLD) and a programmable logic array (PLA).

21. A circuit comprising:

a programmable logic circuit, wherein said programmable logic circuit is configured to (i) receive one or more external inputs, (ii) receive signals from an I/O macrocell and a buried macrocell, and (iii) present signals to said I/O macrocell and buried macrocell;

a microcontroller connected to said programmable logic circuit through a first bus, wherein said programmable logic circuit comprises a programmable interconnect matrix that connects one or more of an address, a control and a data out signal to said microcontroller; and

a memory array connected to said microcontroller through a second bus, wherein said microcontroller, said programmable circuit, said first bus, said second bus and said memory array are fabricated as a single integrated circuit chip.