Memory cell with fuse element

• US 6,898,103 B2
• Filed: 01/28/2003
• Issued: 05/24/2005
• Est. Priority Date: 11/03/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Smith, Douglas D., Vasiliu, Laurentiu, Buer, Myron, Radieddine, Bassem
• Primary Examiner(s): Lam, David
• Application Number:
  US10/352,417
• Publication Number:
  US 20030142530A1
• Time in Patent Office: 847 Days
• Field of Search: 365/189.11, 365/96, 365/225.7, 365/189.12, 365/103, 365/104, 365/161
• US Class Current: 365/96
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/18 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 8/16 Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups

Abstract

The present invention relates to a programmable memory cell and a method of setting a state for a programmable memory cell. The memory cell includes two thin gated fuses adapted to set the state of the memory cell. A level shifter device is connected to the gated fuses and is adapted to stand off a high voltage when setting the state of the memory cell. At least one switch transistor is connected to at least the level shifter device and is adapted to select at least one of the gated fuses, enabling a high voltage to be communicated thereto, thus setting the state of the memory cell.

Claims

1. A memory device comprising:

at least a gate-ox fuse element adapted to selectively set a state of the memory device; and

at least a level shifter adapted to standoff a high voltage required to set said state of the memory device.

2. The memory device of claim 1, wherein said gate-ox fuse element comprises at least two coupled Nfet transistors.

3. The memory device of claim 1, wherein said gate-ox fuse element is a thin gate-ox fuse element.

4. The memory device of claim 3, wherein an oxide of said thin gate-ox fuse element is about 2.5 nm thick or less.

5. The memory device of claim 1 further comprising at least one storage element coupled to at least said gate-ox fuse element and adapted to store data.

6. The memory device of claim 1, wherein said level shifter comprises at least one NFet transistor adapted to standoff said high voltage to at least one other NFet transistor in the memory device.

7. The memory device of claim 1, wherein said level shifter comprises at least one NFET transistor adapted to standoff said high voltage to at least one other NFet transistor in the memory device.

8. The memory device of claim 1 further comprising a programming device adapted to set said state of the memory device.

9. The memory device of claim 8, wherein said programming device comprises at least one switch transistor adapted to select at least a portion of said gate-ox fuse element, enabling a high voltage to be communicated thereto.

10. The memory device of claim 8, wherein said programming device comprises at least one transistor adapted to keep at least a portion of said gate-ox fuse element low when setting said state of the memory device.

11. The memory device of claim 1, wherein said level shifter comprises at least one NFet transistor adapted to standoff said high voltage to at least one other NFet transistor in the memory cell.

12. A programmable memory cell comprising:

two gated fuses adapted to set a state of the memory cell;

a level shifter connected to said gated fuses and adapted to stand off a high voltage when setting said state of the memory cell; and

at least one switch transistor connected to at least said level, shifter adapted to select at least one of said gated fuses and enable a high voltage to be communicated thereto, setting said state of the memory cell.

13. The memory cell of claim 12 further comprising a programming device adapted to keep at least one of the gated fuses low when setting said state of the memory cell.

14. The memory cell of claim 12, wherein said gated fuses are thin oxide gated fuses.

15. The memory cell of claim 14, wherein an oxide of said thin oxide gated fuse is about 2.5 nm thick or less.

16. The memory cell of claim 12, wherein said level shifter comprises at least one PFet transistor adapted to standoff said high voltage to at least one other PFet transistor in the memory cell.

17. A method of programming a memory device comprising:

selectively setting a state of the memory device using at least a gate-ox fuse element; and

standing off a high voltage required to set said state of the memory device.

18. The method of claim 17, wherein standing off said high voltage comprises standing off said high voltage to at least one NFet transistor in the memory cell using a level shifter having at least one NFet transistor.

19. The method of claim 17, wherein standing off said high voltage comprises standing off said high voltage to at least one PFet transistor in the memory cell using a level shifter having at least one PFet transistor.

20. The method of claim 17 further comprising selecting at least a portion of said gate-ox fuse element, enabling a high voltage to be communicated thereto.

21. The method of claim 17 further comprising keeping at least a portion of said gate-ox fuse element low when setting said state of the memory device.