Multi-bit-per-cell flash EEPROM memory with refresh

• US 6,898,117 B2
• Filed: 10/18/2001
• Issued: 05/24/2005
• Est. Priority Date: 09/08/1997
• Status: Expired due to Fees

• Current Assignee: SanDisk Corporation (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: So, Hock C., Wong, Sau C.
• Primary Examiner(s): Lam, David
• Application Number:
  US10/045,505
• Publication Number:
  US 20030021149A1
• Time in Patent Office: 1,314 Days
• Field of Search: 365/185.09, 365/185.24, 365/185.25, 365/185.03, 365/184, 714/721, 371/21.4, 371/21.1
• US Class Current: 365/185.03
• CPC Class Codes: B64C 27/006 Safety devices
• CPC Class Codes: G01N 29/14 using acoustic emission techniques echo of particles G01N29/046; measuring mechanical vibrations or acoustic waves in solids in general G01H1/00
• CPC Class Codes: G01N 29/227 related to high pressure, tension or stress conditions
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5635 Erasing circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells
• CPC Class Codes: G11C 2211/5634 Reference cells
• CPC Class Codes: G11C 29/00 Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50004 of threshold voltage

Abstract

A memory architecture for a non-volatile analog or multiple-bits-per-cell memory includes multiple separate memory arrays and multiple read/write pipelines. The multiple read/write pipelines share a read circuit and/or a write circuit to reduce the circuit area of each pipeline and the circuit area of the memory as a whole. In one embodiment, a shared write circuit generates a programming voltage that changes with an input signal representing values to be written to the memory. Each pipeline includes a sample-and-hold circuit that samples the programming voltage when the pipeline begins a write operation. The write circuit can additionally generate a verify voltage that a second sample-and-hold circuit in each pipeline samples when starting a write operation.

Claims

1. A method of operating a multi-state non-volatile memory, wherein each of said multi-states is identified with a corresponding one of a plurality distinct non-contiguous threshold voltage ranges, the method comprising:

identifying a memory cell as having a threshold voltage in a range intermediate to the threshold voltage ranges corresponding to a first of said multi-states and a second of said multi-states, wherein the first and second multi-states correspond to adjacent ones of said distinct non-contiguous threshold voltage ranges;

writing the identified memory cell to have a threshold voltage in the range corresponding to one of said first and second multi-states.

2. The method of claim 1, wherein in response to said identifying a memory cell determining that the identified memory cell has a threshold voltage in a portion of said intermediate range that is adjacent to the one of the first and second multi-states having the higher threshold voltage range, said writing writes the identified memory cell to said one of the first and second multi-states having the higher threshold.

3. The method of claim 2, wherein in response to said identifying a memory cell determining that the identified memory cell has a threshold voltage in a portion of said intermediate range that is adjacent to the one of the first and second multi-states having the lower threshold voltage range, said writing writes the identified memory cell to said one of the first and second multi-states having the lower threshold.

4. The method of claim 3, wherein said writing includes:

erasing said identified memory cells; and

subsequently programming said identified memory cell to have a threshold voltage in the range corresponding to said one of the first and second multi-states having the lower threshold.

5. The method of claim 1, wherein said identified memory cell belongs to a sector of cells and wherein said writing the identified memory cell is performed as part of writing all of the cells in said sector.

6. The method of claim 5, wherein said writing all of the cells in said sector comprises:

copying said sector to a buffer memory;

altering in the buffer memory the data of content of the identified memory cell to correspond to said one of said first and second multi-states; and

programming said sector back into the non-volatile memory.

7. The method of claim 6, wherein said sector is programmed back into the same physical sector from which it was copied.

8. The method of claim 6, wherein said sector is programmed into a different physical sector than that from which it was copied.

9. The method of claim 5, wherein in response to said identifying a memory cell, a flag associated with the sector to which the identified memory cells belongs is set;

and wherein the writing of said sector is performed in response to said flag being set.

10. The method of claim 9, wherein said writing of the sector performed in response to said flag being set is performed during a period when the memory is inactive.

11. The method of claim 1, wherein said method is performed as part of a systematic refresh process.

12. The method of claim 1, wherein said memory cell is an EEPROM memory cell.