Deep wordline trench to shield cross coupling between adjacent cells for scaled NAND

• US 6,898,121 B2
• Filed: 01/28/2003
• Issued: 05/24/2005
• Est. Priority Date: 06/19/2002
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Chien, Henry, Fong, Yupin
• Primary Examiner(s): Hoang, Huan
• Application Number:
  US10/353,570
• Publication Number:
  US 20040012998A1
• Time in Patent Office: 847 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.19
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A NAND flash memory structure with a wordline or control gate that provides shielding from Yupin effect errors and generally from potentials in adjacent strings undergoing programming operations with significant variations in potential.

Claims

1. A flash memory device formed from a substrate, the device comprising:

strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above channel regions in the substrate and separated from the channel regions,

wherein adjacent first and second strings undergo programming operations at the same time, and wherein when programming a selected cell of the first string, any change in the potential in the second adjacent string is shielded from the first string by a wordline extending across adjacent strings and extending between the floating gates of the first and second strings into a shallow trench isolation area between the channel regions of adjacent strings to shield a floating gate of the first string from a potential of the second adjacent string.

2. The flash memory device of claim 1 wherein the wordline shields the floating gate of the first string from a potential in the substrate at an adjacent second string.

3. The flash memory device of claim 1 wherein the wordline shields the floating gate of the first string from a potential of the adjacent floating gate of the second string.

4. The flash memory device of claim 1 further comprising a gate oxide layer between the floating gates and the substrate, the wordline extending down past the level of an upper surface of the gate oxide layer.

5. The flash memory device of claim 1 wherein the wordline shields the floating gate of the first string from the potential of a floating gate of the second adjacent string.

6. A flash memory device comprising:

strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above a substrate;

shallow trench isolation areas between the strings;

wordlines extending across adjacent strings and extending between the floating gates into the shallow trench isolation areas between the strings,

wherein in the case of programming adjacent NAND strings, a channel of a first string adjacent a floating gate of a second string is at a first potential for a number of programming pulses and changed to a second potential during subsequent programming pulses, and

wherein the potential of the channel of the first string couples to the potential of the floating gate of the second string, and

wherein the wordlines shield the floating gate of the second string from the potential of the channel of the first string.

7. The flash memory device of claim 6 further comprising a gate oxide layer between the floating gates and the substrate, the wordlines extending down past the level of an upper surface of the gate oxide layer.

8. The flash memory device of claim 6 wherein the wordlines extend down past the level of an upper surface of the substrate.

9. The flash memory device of claim 6 wherein the wordlines extend down past the lower level of the channel.

10. A flash memory device formed from a substrate, the device comprising:

strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above the substrate,

the floating gates formed above a gate oxide layer formed upon cell channel regions within the substrate;

control gates that extend across adjacent strings and between the floating gates of adjacent strings, each control gate extending down past an upper surface of the substrate to shield a selected floating gate during a read or verify operation from a potential present in an adjacent string.

11. The flash memory device of claim 10 wherein the control gates shield the selected floating gate from the potential of the substrate beneath the adjacent string.

12. The flash memory device of claim 11 wherein the control gates shield the selected floating gate from the potential of a channel region of the substrate beneath the adjacent string.

13. The flash memory device of claim 10 wherein the control gates shield the selected floating gate from the potential of the floating gates of the adjacent string.

14. A flash memory device formed from a substrate, the device comprising:

strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above the substrate, wherein the strings are separated by shallow trench isolation areas;

two or more discrete programming levels programmed by increasing a programming potential until the levels are reached, wherein once the floating gates have reached a steady state a linear increase in programming potential results in an approximately linear increase in floating gate charge given a constant potential surrounding environment; and

wordlines extending across adjacent strings and extending between the floating gates into the shallow trench isolation areas, such that when a floating gate of a selected string is read or verified, a wordline minimizes deviation from the linear increase due to voltage variations in the surrounding environment.

15. The flash memory device of claim 14 wherein the wordline shields the floating gate of the selected string from voltage variations in an adjacent portion of the substrate.

16. The flash memory device of claim 14 wherein the wordline shields the floating gate of the selected string from voltage variations in an adjacent floating gate.

17. The flash memory device of claim 14 wherein the wordline shields the floating gate of the first string from the potential of the channel region of the second adjacent string.

18. The flash memory device of claim 14 further comprising a gate oxide layer between the floating gates and the substrate, the wordline extending down past the level of an upper surface of the gate oxide layer.

19. The flash memory device of claim 14 wherein the wordline extends down past the level of an upper surface of the substrate.

20. A flash memory device comprising:

strings of adjacent transistors of a NAND architecture comprising a first select gate, a plurality of floating gates, and a second select gate, the plurality of floating gates formed above a substrate;

wherein in the case of programming adjacent NAND strings, a channel of a first string adjacent a floating gate of a second string is at a first potential for a number of programming pulses and changed to a second potential during subsequent programming pulses; and

means for controlling the floating gates and for isolating the floating gates from variations of adjacent potential fields during and between program pulses, the means for controlling the floating gates and for isolating the floating gates extending between the floating gates to or below the upper level of the substrate.

21. In a memory having a plurality of serious strings of memory cells arranged to form columns across a substrate surface and individually including a floating gate, wherein the strings of memory cells are separated by dielectric between them, and wherein a plurality of word lines extend across rows of memory cell floating gates the dielectric therebetween, a method of programming charge levels on an individual row of memory cells to defined states, comprising:

alternatively applying program pulses to and reading the states of memory cells along the row,

in response to reading that a memory cell along the row has reached its defined state, ceasing to apply any further programming pulses to such a memory cell while continuing to apply programming pulses to other memory cells in the row until all of the memory cells along the row have reached their defined states, and

utilizing isolation between the floating gates in the row during the alternate application of program pulses to and reading the state of the memory cells along the row by maintaining the word lines between adjacent floating gates and extending into the dielectric therebetween.

22. The method of claim 21, wherein the dielectric fills trenches formed into the substrate surface between the column strings of memory cells, and providing isolation includes maintaining the word lines in the dielectric within the trenches to a level at least as low as the substrate surface.

23. The method of claim 22, wherein providing isolation includes maintaining the word lines below the level of the substrate surface.

24. The method of claim 21, wherein successive programming pulses are increased in magnitude.

25. The method of claim 21, wherein the number of defined programmed states of the individual memory cells exceeds two.