System and method for adaptively accommodating a high amplitude downstream signal in a DSL modem

• US 6,898,236 B1
• Filed: 09/26/2000
• Issued: 05/24/2005
• Est. Priority Date: 09/26/2000
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: 2Wire, Inc. (CommScope Holding Company, Inc.)
• Inventors: Sun, Ting
• Primary Examiner(s): Tran, Khai
• Application Number:
  US09/670,490
• Time in Patent Office: 1,701 Days
• Field of Search: 375/222, 375/220, 375/259, 375/269, 375/345, 327/270, 327/308, 327/393, 330/82, 330/84, 330/54, 330/144, 330/284, 330/282
• US Class Current: 375/222
• CPC Class Codes: H04B 2203/5408 using protocols
• CPC Class Codes: H04B 3/542 the information being in digital form
• CPC Class Codes: H04L 27/0002 analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: H04L 27/2647 Arrangements specific to the receiver only equalisation H04L27/01

Abstract

A system and method are disclosed for adaptively accommodating a high amplitude downstream signal in a DSL modem. High amplitude downstream signals are common with local loop lengths of less than about 6,000 feet and can saturate DSL modem components and impair DSL service if not effectively accommodated.

In general, a DSL system detects a high amplitude downstream DSL signal and adjusts a DSL modem analog front end in response to the detected high amplitude downstream DSL signal so that analog front end components of a DSL modem are not saturated by the high amplitude downstream DSL signal. Pursuant to one embodiment, a digital signal processor detects the high amplitude DSL signal and, in response, decreases a gain of a first stage receiver to accommodate the high amplitude downstream DSL signal. Another embodiment introduces additional attenuation of the downstream DSL signal to attenuate high amplitude downstream DSL signals before they enter first stage receiver amplifier circuits.

Claims

1. An automatically adjustable DSL modem for adaptively accommodating a high amplitude downstream DSL signal, comprising:

a data processor for determining an amplitude of the downstream DSL signal; and

a first stage receiver coupled to and controlled by the data processor;

the first stage receiver comprising;

an adjustable gain so that the data processor may decrease the gain of the first stage receiver in response to detecting a high amplitude downstream DSL signal; and

a pair of amplifier circuits, each amplifier circuit including a switching device coupled to and controlled by the data processor for selectively switching in additional resistance to decrease the gain of the amplifier circuit in response to detection of a high amplitude downstream DSL signal.

2. The automatically adjustable DSL modem according to claim 1, further comprising an analog front end including a hybrid and a receive filter, the first stage receiver being disposed between the hybrid and the receive filter.

3. An automatically adjustable DSL modem for adaptively accommodating a high amplitude downstream DSL signal, comprising:

a data processor for determining an amplitude of the downstream DSL signal; and

a loss circuit coupled to and controlled by the data processor for attenuating the downstream signal in response to the data processor determining that a high amplitude downstream DSL signal is present, wherein the loss circuit further comprises a switching device coupled to a resistor, the switching device being coupled to and controlled by the data processor to switch in the resistor to selectively attenuate the downstream DSL signal.

4. A DSL modem for converting a downstream DSL analog signal to digital data and for converting digital data to an analog signal, comprising:

a data processor for detecting the amplitude of the downstream analog signal, the data processor being configured to determine whether the amplitude of the downstream analog signal is greater than a predetermined threshold;

an analog front end coupled to and controlled by the data processor for receiving the downstream analog signals;

the date processor being configured to adjust the analog front end according to whether the amplitude of the downstream signal is greater than a predetermined threshold to prevent the analog front end from being saturated by high amplitude downstream signals; and

a passive loss circuit coupled to and controlled by the data processor for attenuating the downstream signal in response to the data processor detecting a downstream signal greater than the predetermined threshold.