Vehicle controller for controlling rewriting data in a nonvolatile memory

• US 6,898,490 B2
• Filed: 10/09/2002
• Issued: 05/24/2005
• Est. Priority Date: 10/09/2001
• Status: Expired due to Fees

• Current Assignee: Honda Giken Kogyo Kabushiki Kaisha (Honda Motor Company)
• Original Assignee: Honda Giken Kogyo Kabushiki Kaisha (Honda Motor Company)
• Inventors: Matsuura, Masanori, Yashiki, Tetsuya
• Primary Examiner(s): Chin, Gary
• Assistant Examiner(s): MANCHO, RONNIE M
• Application Number:
  US10/267,537
• Publication Number:
  US 20030069671A1
• Time in Patent Office: 958 Days
• Field of Search: 701/1, 701/35, 341/50, 711/100, 711/103, 711/154, 711/167, 711/150, 711/155, 711/120
• US Class Current: 701/1
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

A vehicle controller comprises a first buffer for storing at least one data block, a second buffer for storing at least one data block, and a rewritable non-volatile memory for storing information for controlling a vehicle. The controller receives a data block from an external rewriting device to store it in the first buffer. The data block stored in the first buffer is transferred to the second buffer. The data block stored in the second buffer is written into the memory. When a first data block is written into the memory, a subsequent data block is received. Thus, the time required to rewrite data stored in the nonvolatile memory is reduced.

Claims

1. A vehicle controller comprising:

a first buffer for storing at least one data block;

a second buffer for storing at least one data block;

a rewritable nonvolatile memory for storing information for controlling a vehicle;

means for receiving a data block from an external rewriting device to store it in the first buffer;

means for transferring the data block stored in the first buffer to the second buffer;

means for writing the data block stored in the second buffer into the memory;

wherein when said means for writing is writing a first data block into the memory, said means for receiving receives a subsequent data block.

2. The vehicle controller of claim 1, wherein the receiving means starts receiving the subsequent data block from the external rewriting device in response to completion of transferring the first data block.

3. The vehicle controller of claim 1, wherein the receiving means determines whether there is free space in the first buffer;

wherein, if there is free space in the first buffer, the receiving means starts receiving the subsequent data block from the external rewriting device.

4. The vehicle controller of claim 1, wherein the transfer means starts transferring the subsequent data block from the first buffer to the second buffer in response to completion of writing the first data block into the memory.

5. The vehicle controller of claim 1, wherein, after writing the first data block into the memory is completed, the writing means starts writing the subsequent data block into the memory if the subsequent data block is stored in the second buffer by the transfer means;

whereby a delay between an end of writing the first data block and a start of writing the subsequent data block is equal to or less than a time required to transfer the subsequent data block from the first buffer to the second buffer.

6. The vehicle controller of claim 1, wherein, after receiving the first data block is completed, the receiving means starts receiving the subsequent data block if free space is produced in the first buffer by the transfer means;

whereby a delay between an end of receiving the first data block and a start of receiving the subsequent data block is equal to or less than a time required to transfer the first data block from the first buffer to the second buffer.

7. The vehicle controller of claim 1, further comprising at least one intermediate buffer provided between the first buffer and the second buffer;

wherein the transfer means further comprises a first transfer means for transferring a data block stored in the first buffer to the intermediate buffer and a second transfer means for transferring the data block stored in the intermediate buffer to the second buffer;

wherein the first transfer means starts transferring the subsequent data block if transferring the first data block from the intermediate buffer to the second buffer is completed to produce free space in the intermediate buffer;

wherein the second transfer means starts transferring the subsequent data block if writing the first data block into the memory is completed to produce free space in the second buffer.

8. The vehicle controller of claim 1, wherein the first and second buffers are implemented by a memory having an access time faster than the nonvolatile memory.

9. A method for rewriting a rewritable nonvolatile memory included in a vehicle controller, the memory storing information for controlling a vehicle, the vehicle controller comprising a first buffer storing at least one data block and a second buffer for storing at least one data block, the method comprising:

(a) receiving a data block from an external rewriting device to store it in the first buffer;

(b) transferring the data block stored in the first buffer to the second buffer;

(c) writing the data block stored in the second buffer into the memory;

wherein when the step (c) for a first data block is performed, the step (a) for a subsequent data block is performed.

10. The method of claim 9, wherein the step (a) for the subsequent data block is started in response to completion of transferring the first data block.

11. The method of claim 9, wherein the step (a) for the subsequent data block further comprises determining whether there is free space in the first buffer;

wherein, if there is free space in the first buffer, the step (a) for the subsequent data block is started.

12. The method of claim 9, wherein the step (b) for the subsequent data block is started in response to completion of writing the first data block into the memory.

13. The method of claim 9, wherein the step (b) for the subsequent data block further includes erasing the subsequent data block from the first buffer in response to completion of transferring the subsequent data block.

14. The method of claim 9, wherein the step (c) for the subsequent data block further includes erasing the subsequent data block from the second buffer in response to completion of writing the subsequent data block into the memory.

15. The method of claim 9, wherein the step (b) for the subsequent data block is started in response to completion of writing the first data block into the memory;

wherein the step (c) for the subsequent data block is started in response to completion of transferring the subsequent data block;

whereby a delay between an end of writing the first data block and a start of writing the subsequent data block is equal to or less than a time required to transfer the subsequent data block from the first buffer to the second buffer.

16. The method of claim 9, wherein the step (b) for the first data block is started in response to completion of receiving the first data block;

wherein the step (a) for the subsequent data block is started in response to completion of transferring the first data block;

whereby a delay between an end of receiving the first data block and a start of receiving the subsequent data block is equal to or less than a time required to transfer the first data block from the first buffer to the second buffer.

17. The method of claim 9, wherein the second buffer stores two or more data blocks;

wherein the step (b) for the subsequent data block is started in response to completion of receiving the subsequent data block;

wherein the step (c) for the subsequent data block is started in response to completion of writing the first data block into the memory;

whereby there is no delay between an end of writing the first data block and a start of writing the subsequent data block.

18. The method of claim 9, wherein the first buffer stores two or more data blocks;

wherein the step (a) for the subsequent data block is started in response to completion of receiving the first data block;

whereby there is no delay between an end of receiving the first data block and a start of receiving the subsequent data block.

19. The method of claim 9, wherein an intermediate buffer is provided between the first buffer and the second buffer;

wherein the transfer step (b) further comprises;

(b1) transferring a data block stored in the first buffer to the intermediate buffer; and

(b2) transferring the data block stored in the intermediate buffer to the second buffer;

wherein the second transfer step (b1) for the subsequent data block is started in response to completion of transferring the first data block from the intermediate buffer to the second buffer;

wherein the first transfer step (b2) for the subsequent data block is started in response to completion of writing the first data block into the memory.

20. The method of claim 19, wherein the step (b1) further comprises erasing the first data block from the first buffer to produce free space in the first buffer in response to completion of transferring the first data block from the first buffer to the intermediate buffer,

wherein the step (b2) further comprises erasing the first data block from the intermediate buffer to produce free space in the intermediate buffer in response to completion of transferring the first data block from the intermediate buffer to the second buffer.