Multiport high speed communications integrated circuit
First Claim
Patent Images
1. An integrated circuit comprising:
- a high speed bus interface to interface to a core chipset through a high speed bus;
a serial mass data storage host adapter in communication with the high speed bus interface to control a high speed mass data storage unit;
wherein the serial mass data storage host adapter controls the high speed mass data storage unit in response to a signal from the core chipset; and
a network controller in communication with the high speed bus interface to control a network port.
4 Assignments
0 Petitions
Accused Products
Abstract
An integrated circuit for multi-port communications is provided. The integrated circuit includes a high speed bus interface to interface to a core chipset through a high speed bus. A serial mass data storage host adapter is in communication with the high speed bus interface to control a high speed mass data storage unit. A network controller is in communication with the high speed bus interface to control a network port.
-
Citations
39 Claims
-
1. An integrated circuit comprising:
-
a high speed bus interface to interface to a core chipset through a high speed bus;
a serial mass data storage host adapter in communication with the high speed bus interface to control a high speed mass data storage unit;
wherein the serial mass data storage host adapter controls the high speed mass data storage unit in response to a signal from the core chipset; and
a network controller in communication with the high speed bus interface to control a network port. - View Dependent Claims (2, 3)
-
-
4. An integrated circuit comprising:
-
a high speed bus interface to interface to a core chipset through a high speed bus;
a serial mass data storage host adapter in communication with the high speed bus interface to control a high speed mass data storage unit; and
a network controller in communication with the high speed bus interface to control a network port;
wherein the network controller includes an Ethernet controller having an operating speed of at least 1 Giga Bit per second. - View Dependent Claims (5, 6, 7)
-
-
8. An integrated circuit comprising:
-
a high speed bus interface to interface to a core chipset through a high speed bus;
wherein the high speed bus interface is selected from the group comprising at least one of a PCI-X bus interface, a HyperTransport bus interface, a 3GIO bus interface, and an Infiniband bus interfaces;
a serial mass data storage host adapter in communication with the high speed bus interface to control a high speed mass data storage unit; and
a network controller in communication with the high speed bus interface to control a network port. - View Dependent Claims (9, 10)
-
-
11. An integrated circuit to communicate information with a core chipset over a high speed bus, comprising:
-
means for bus interfacing to the core chipset through the high speed bus;
means for controlling a high speed mass data storage unit, the controlling means in communication with the bus interfacing means and the high speed mass data storage unit;
wherein the controlling means controls the high speed mass data storage unit in response to a signal from the core chipset; and
means for network interfacing to a network port, the network interfacing means in communication with the bus interfacing means and the network port. - View Dependent Claims (12, 13)
-
-
14. An integrated circuit to communicate information with a core chipset over a high speed bus, comprising:
-
means for bus interfacing to the core chipset through the high speed bus;
means for controlling a high speed mass data storage unit, the controlling means in communication with the bus interfacing means and the high speed mass data storage unit; and
means for network interfacing to a network port, the network interfacing means in communication with the bus interfacing means and the network port;
wherein the means for network controlling interfacing includes a high speed Ethernet controller having an operating speed of at least 1 Giga Bit per second. - View Dependent Claims (15, 16, 17)
-
-
18. An integrated circuit to communicate information with a core chipset over a high speed bus, comprising:
-
means for bus interfacing to the core chipset through the high speed bus;
wherein the bus interfacing means is selected from the group comprising at least one of a PCI-X bus interface, a HyperTransport bus interface, a 3GIO bus interface, and an Infiniband bus interface;
means for controlling a high speed mass data storage unit, the controlling means in communication with the bus interfacing means and the high speed mass data storage unit; and
means for network interfacing to a network port, the network interfacing means in communication with the bus interfacing means and the network port. - View Dependent Claims (19, 20)
-
-
21. A method of communicating information with a data storage unit and a network port, comprising:
-
providing, in a semiconductor circuit, a high speed bus interface to interface to a core chipset through a high speed bus;
providing a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset;
wherein the serial ATA host adapter controls the data storage unit in response to a signal from the core chipset; and
providing a high speed Ethernet network controller in communication with the high speed bus interface to control the network port.
-
-
22. A method of communicating information with a data storage unit and a network port, comprising:
-
providing in a semiconductor circuit, a high speed bus interface to interface to a core chipset through a high speed bus;
providing a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset; and
providing a high speed Ethernet network controller in communication with the high speed bus interface to control the network port;
wherein the high speed Ethernet network controller has an operating speed of at least 1 Giga Bit per second.
-
-
23. A method of communicating information with a data storage unit and a network port, comprising:
-
providing, in a semiconductor circuit, a high speed bus interface to interface to a core chipset through a high speed bus;
providing a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset; and
providing a high speed Ethernet network controller in communication with the high speed bus interface to control the network port;
wherein the high speed Ethernet network controller includes a MAC layer and a physical layer.
-
-
24. A method of communicating information with a data storage unit and a network port, comprising:
-
providing in a semiconductor circuit, a high speed bus interface to interface to a core chipset through a high speed bus;
wherein the high speed bus interface is selected from the group comprising at least one of a PCI-X bus interface, a HyperTransport bus interface, a 3GIO bus interface and an Infiniband bus interfaces;
providing a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset; and
providing a high speed Ethernet network controller in communication with the high speed bus interface to control the network port.
-
-
25. An integrated circuit to communicate information between a core chipset and a network port and a data storage unit over a high speed bus, comprising:
-
a high speed bus interface to interface to the core chipset through the high speed bus;
wherein the high speed bus interface is selected from the group comprising at least one of a PCI-X bus interface, a HyperTransport bus interface, a 3GIO bus interface and an Infiniband bus interfaces;
a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset; and
a high speed Ethernet network controller in communication with the high speed bus interface to control the network port.
-
-
26. An integrated circuit to communicate information between a core chipset and a network port and a data storage unit over a high speed bus, comprising:
-
a high speed bus interface to interface to the core chipset through the high speed bus;
a serial ATA host adapter in communication with the high speed bus interface to control the data storage unit in response to a signal from the core chipset; and
a high seed Ethernet network controller in communication with the high speed bus interface to control the network port;
wherein the high speed Ethernet network controller has an operating speed of at least 1 Giga Bit per second. - View Dependent Claims (27)
-
-
28. An integrated circuit to communicate information between a core chipset and a network port and a data storage unit over a high speed bus, comprising:
-
means for bus interfacing to the core chipset through the high speed bus;
means for controlling the data storage unit, the controlling means to provide communication between the bus interfacing means and the data storage unit in response to a signal from the core chipset; and
means for network interfacing to a network port, the network interfacing means in communication with the bus interfacing means and the network port. - View Dependent Claims (29, 30, 31)
-
-
32. A multi-port integrated circuit to communicate information between a core chipset and at least two peripheral devices over a high speed bus, the two peripheral devices including a data storage unit and a network device, comprising:
-
a high speed bus interface to interface to the core chipset through the high speed bus;
a serial ATA host adapter in communication with the high speed bus interface and a first port to control the data storage unit in response to a signal from the core chipset; and
a high speed Ethernet network controller in communication with the high speed bus interface and a second port to control the network device. - View Dependent Claims (33, 34, 35)
-
-
36. A multi-port integrated circuit to communicate information between a core chipset and at least two peripheral devices over a high speed bus, the two peripheral devices including a data storage unit and a network device, comprising:
-
means for bus interfacing to the core chipset through the high speed bus;
means for controlling the data storage unit in serial communication with the high speed bus interface and a first port to control the data storage unit in response to a signal from the core chipset; and
means for network interfacing to a second port, the network interfacing means in communication with the high speed bus interface and the second port to control the network device. - View Dependent Claims (37, 38, 39)
-
Specification