Shared memory with programmable size

• US 6,898,678 B1
• Filed: 06/09/2000
• Issued: 05/24/2005
• Est. Priority Date: 06/09/1999
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Ollivier, Gerald, Mazzocco, Daniel, Six, Laurent, Laine, Armelle
• Primary Examiner(s): BATAILLE, PIERRE MICHE
• Application Number:
  US09/591,615
• Time in Patent Office: 1,810 Days
• Field of Search: 711150-153, 711/158, 711/170, 711/147, 711/100, 711/115, 711/163, 710/22, 710/39, 710/40, 710/244, 710/107, 710/305, 709/217
• US Class Current: 711/151
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A digital system is provided with a memory (42) that can be shared by two or more data requestors (10, 20). Two modes of access are provided. In a shared access memory (SAM) access mode, all of the data requestors can sequentially access the memory. In a host only memory (HOM) access mode, a portion (42a) of the memory is connected directly to one of the requestors, such, as a host processor (10), so that high bandwidth transfers can be performed. A portion (42b) that is not selected to be in HOM mode can be accessed by other requestors or shut down to save power. The size (S1) of the portion of memory selected for HOM mode is selected to match the requirements of a given application and can be changed by writing a size value to a register.

Claims

1. A digital system, comprising:

a memory circuit;

a first requester circuit with a first memory access node;

a second requester circuit with a second memory access node;

a scheduling circuit connected to the first memory access node and to the second memory access node and having a request output node, operable to sequentially schedule memory accesses to the memory circuit by the first requestor circuit and by the second request circuit;

a selection circuit connected to the first memory access node and to the scheduling circuit request output node with an output node connected to the memory circuit;

access mode circuitry for indicating at least a first access mode and a second access mode controllably connected to the selection circuit, such that both the first requester circuit and the second requestor circuit can sequentially access the memory circuit when the access mode circuitry indicates the first access mode and the first requester circuit has exclusive access to the memory circuit when the access mode circuitry indicates the second access mode; and

a size register for holding a size parameter coupled to the selection circuit, the selection circuit being operable to select a first portion of the memory circuit in response to the size parameter when the access mode circuitry indicates the second access mode, wherein only the first portion of the memory circuit is operable for exclusive access by the first requestor when the access mode circuitry indicates the second access mode.

2. The digital system of claim 1, wherein a second portion of the memory circuit not selected in response to the size parameter is operable to be in a low power mode when the access mode circuitry indicates the second access mode.

3. The digital system according to claim 1, wherein the selector circuit is operable such that a second portion of the memory circuit not selected in response to the size parameter can be accessed by the second requester when the access mode circuitry indicates the second access mode.

4. The digital system according to claim 1, wherein the size parameter is ignored when the access mode circuitry indicates the first access mode such that the entire memory circuit is operable to be selected for sequential access by the first requester and the second requestor.

6. The digital system according to claim 1, wherein the first requester circuit is a host processor and the second requester circuit is direct memory access circuit channel controller.

5. A digital system comprising:

a memory circuit;

a first requester circuit with a first memory access node;

a second requestor circuit with a second memory access node;

a scheduling circuit connected to the first memory access node and to the second memory access node and having a request output node, operable to sequentially schedule memory accesses to the memory circuit by the first requester circuit and by the second request circuit;

a selection circuit connected to the first memory access node and to the scheduling circuit request output node with an output node connected to the memory circuit;

access mode circuitry for indicating at least a first access mode and a second access mode controllably connected to the selection circuit, such that both the first requestor circuit and the second requestor circuit can sequentially access the memory circuit when the access mode circuitry indicates the first access mode and the first requester circuit has exclusive access to the memory circuit when the access mode circuitry indicates the second access mode;

a size register for holding a size parameter coupled to the selection circuit, the selection circuit being operable to select a first portion of the memory circuit in response to the size parameter when the access mode circuitry indicates the second access mode, wherein only the first portion of the memory circuit is operable for exclusive access by the first requester when the access mode circuitry indicates the second access mode; and

a clock circuit connected to the second requestor and to the memory circuit, wherein the first portion of the memory circuit operates synchronously with the clock circuit when the access mode circuitry indicates the first access mode and wherein the first portion of the memory circuit operates in an asynchronous manner when the access mode circuitry indicates the second access mode.

7. A method of operating a digital system having a memory circuit that is shared by a plurality of requestor circuits, comprising the steps of:

sharing access to the memory circuit between the plurality of requester circuits when the digital system is in a first mode of operation;

selecting a first portion of the memory circuit responsive to a size parameter stored in a register, such that a second portion of the memory circuit is not selected; and

limiting access to the first portion of memory circuit to only a first requestor of the plurality of requestors when the digital system is in a second mode of operation.

8. The method of claim 7, further comprising the step of sharing access to the second portion of the memory circuit between the plurality of requestor circuits when the digital system is in the second mode of operation.

9. The method of claim 7, further comprising the step of placing the second portion of the memory circuit in a low power mode when the digital system is in the second mode of operation.

10. The method of claim 7, wherein the memory has a total size equal to the sum of the first portion and the second portion.

11. The method of claim 10, further comprising the step of storing a different size parameter in the register, such that the step of selecting results in a first portion having a different size in response to the different size parameter.