Efficient method for mode change detection and synchronization

• US 6,898,697 B1
• Filed: 03/29/2002
• Issued: 05/24/2005
• Est. Priority Date: 03/29/2002
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Clark, Michael T., Gao, Hongwen, Keltcher, Chetana N.
• Primary Examiner(s): PAN, DANIEL H
• Application Number:
  US10/113,387
• Time in Patent Office: 1,152 Days
• Field of Search: 712/219, 712/225, 712/229, 712/33, 712/203, 712/210, 712/227, 712/211, 711/201, 711/208, 711/209, 711/212, 710/33
• US Class Current: 712/229
• CPC Class Codes: G06F 9/30076 to perform miscellaneous control operations, e.g. NOP
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30189 according to execution mode, e.g. mode flag
• CPC Class Codes: G06F 9/342 Extension of operand address space
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00

Abstract

A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations. A read of the special register may then be performed in order to determine whether a state change is indicated.

Claims

1. A method comprising:

detecting a control transfer operation in a processor;

determining whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;

performing a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and

performing a second check in response to detecting the operating mode is the second mode as a result of the transfer operation;

wherein the first check comprises a limit check and the second check comprises a canonical check; and

flushing a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation.

2. The method of claim 1, wherein the control transfer operation comprises a far transfer instruction.

3. The method of claim 2, wherein segmentation is enabled in the first mode and segmentation is not enabled in the second mode.

4. The method of claim 3, wherein the second mode is a 64-bit addressing mode.

5. The method of claim 1, further comprising reading a register configured to indicate a change in segmentation state as a result of said transfer operation.

6. The method of claim 5, wherein said register is further configured to indicate a change in privilege level as a result of said transfer operation.

7. The method of claim 5, wherein said register is a programmer invisible special register which is accessed via a special register bus.

8. A processor comprising:

a memory configured to store instructions;

first circuitry configured to decode and detect a control transfer instruction; and

second circuitry configured to;

determine whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;

perform a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and

perform a second check in response to detecting the operating mode is the second mode as a result of the transfer operation; and

flush a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation;

wherein the first check comprises a limit check and the second check comprises a canonical check.

9. The processor of claim 8, wherein the control transfer operation comprises a far transfer instruction.

10. The processor of claim 9, wherein the second circuitry comprises a load/store unit.

11. The processor of claim 10, wherein the load/store unit is configured to read a register which is configured to indicate a change in segmentation state as a result of the transfer operation.

12. The processor of claim 11, wherein said register is further configured to indicate a privilege level subsequent to execution of the transfer operation.

13. The processor of claim 11, further comprising a special register file, and wherein said register is a programmer invisible special register included in the special register file and is accessed via a special register bus.

14. The processor of claim 8, wherein segmentation is enabled in the first mode and segmentation is not enabled in the second mode.

15. The processor of claim 14, wherein the second mode is a 64-bit addressing mode.

16. A computer system comprising:

a main memory; and

a processor coupled to the main memory, wherein said processor includes;

an instruction cache configured to store instructions;

a first circuit configured to detect a control transfer instruction; and

a second circuit configured to;

determine whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;

perform a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and

perform a second check in response to detecting the operating mode is the second mode as a result of the transfer operation; and

flush a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation;

wherein the first check comprises a limit check and the second check comprises a canonical check.

17. The computer system of claim 16, wherein the control transfer instruction comprises a far transfer, and wherein segmentation is enabled in the first mode and segmentation is not enabled in the second mode.

18. The computer system of claim 17, wherein the second mode comprises a 64-bit addressing mode.