Efficient method for mode change detection and synchronization
First Claim
1. A method comprising:
- detecting a control transfer operation in a processor;
determining whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;
performing a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and
performing a second check in response to detecting the operating mode is the second mode as a result of the transfer operation;
wherein the first check comprises a limit check and the second check comprises a canonical check; and
flushing a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation.
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Abstract
A processor is configured to operate in a modes which utilize segmentation and which do not utilize segmentation. The processor includes circuitry which is configured to detect and respond to mode and state changes. The circuitry is configured to determine whether a segmentation state of the processor changes in response to execution of a control transfer operation. If the segmentation state does not change as a result of the transfer instruction, execution of instructions may continue sequentially and a corresponding first check performed. However, if the segmentation state does change as a result of the transfer instruction, a flush of the pipeline is initiated prior to performing a corresponding second check. When a first mode of operation is detected a limit check may be performed, while a canonical check may performed when a second mode of operation is detected. A special register is defined which is configured to indicate changes in segmentation state subsequent to a control transfer operations. A read of the special register may then be performed in order to determine whether a state change is indicated.
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Citations
18 Claims
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1. A method comprising:
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detecting a control transfer operation in a processor;
determining whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;
performing a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and
performing a second check in response to detecting the operating mode is the second mode as a result of the transfer operation;
wherein the first check comprises a limit check and the second check comprises a canonical check; and
flushing a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A processor comprising:
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a memory configured to store instructions;
first circuitry configured to decode and detect a control transfer instruction; and
second circuitry configured to;
determine whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;
perform a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and
perform a second check in response to detecting the operating mode is the second mode as a result of the transfer operation; and
flush a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation;
wherein the first check comprises a limit check and the second check comprises a canonical check. - View Dependent Claims (9, 10, 11, 12, 13, 14, 15)
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16. A computer system comprising:
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a main memory; and
a processor coupled to the main memory, wherein said processor includes;
an instruction cache configured to store instructions;
a first circuit configured to detect a control transfer instruction; and
a second circuit configured to;
determine whether an operating mode of the processor changes from a first mode to a second mode in response to execution of the transfer operation;
perform a first check in response to detecting the operating mode is the first mode as a result of the transfer operation; and
perform a second check in response to detecting the operating mode is the second mode as a result of the transfer operation; and
flush a pipeline of the processor in response to detecting the operating mode of the processor changes as a result of the operation;
wherein the first check comprises a limit check and the second check comprises a canonical check. - View Dependent Claims (17, 18)
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Specification