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Clock generation systems and methods

  • US 6,898,721 B2
  • Filed: 06/22/2001
  • Issued: 05/24/2005
  • Est. Priority Date: 06/22/2001
  • Status: Active Grant
First Claim
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1. A low power a reconfigurable processor core, comprising:

  • a plurality of processor units, each unit having a clock input that controls the performance of the unit;

    a wireless transceiver transmitting and receiving at a frequency based on a wireless clock input; and

    a controller having a plurality of clock outputs each coupled to the clock input of the each processor unit, the controller varying the clock frequency of each processor unit and the wireless clock input, the clock outputs being generated from a common master clock.

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