Apparatus and methods for combinational error detection in an InfiniBand switch

• US 6,898,752 B2
• Filed: 05/31/2002
• Issued: 05/24/2005
• Est. Priority Date: 05/31/2002
• Status: Expired due to Fees

• Current Assignee: Microsemi Storage Solutions (U.S.), Inc. (Microchip Technology Incorporated)
• Original Assignee: Agilent Technologies, Inc.
• Inventors: Tucker, S. Paul
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US10/161,503
• Publication Number:
  US 20030226085A1
• Time in Patent Office: 1,089 Days
• Field of Search: 714/752, 714/776, 370/242, 370/235, 370/252, 370/360, 370/474
• US Class Current: 714/752
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.

Claims

1. A combination error detector to detect errors in an InfiniBand packet, the detector comprising:

a register that stores fields of an InfiniBand packet as the packet is being received; and

comparison logic that, as the fields are stored in the register, compares the fields with check values and when an error is detected sets a flag corresponding to the error.

2. The combinational error detector, as set forth in claim 1, further comprising:

packet status logic that identifies the start of a packet and counts the words received in the packet; and

wherein the fields to be stored in the register are determined based on the start of the packet and the word count as identified by the packet status logic.

3. The combinational error detector, as set forth in claim 1, further comprising:

an error flag handler that stores the flags set for each packet and upon completion of the comparisons by the comparison logic prioritizes the flags based on the InfiniBand Architecture Specification.

4. The combinational error detector, as set forth in claim 1, further comprising:

a second register that stores values to be compared with the fields in the register by the comparison logic.

5. The combinational error detector, as set forth in claim 1, further comprising:

an error flag handler that outputs an indication that the packet should be discarded or truncated when a predetermined error flag is set by the comparison logic.

6. An InfiniBand switch comprising:

a hub that redirects incoming packets;

a port that receives incoming packets, performs concurrent combinational error detection on the incoming packets and discards those packets that have a predetermined error.

7. The InfiniBand switch, as set forth in claim 6, wherein the port comprises:

a combination error detector to detect errors in an InfiniBand packet, the detector including;

a register that stores fields of an InfiniBand packet as the packet is being received; and

comparison logic that, as the fields are stored in the register, compares the fields with check values and when an error is detected sets a flag corresponding to the error.

8. The InfiniBand switch, as set forth in claim 7, wherein the combinational error detector further comprises:

packet status logic that identifies the start of a packet and counts the words received in the packet; and

wherein the fields to be stored in the register are determined based on the start of the packet and the word count as identified by the packet status logic.

9. The InfiniBand switch, as set forth in claim 7, wherein the combinational error detector further comprises:

an error flag handler that stores the flags set for each packet and upon completion of the comparisons by the comparison logic prioritizes the flags based on the InfiniBand Architecture Specification.

10. The InfiniBand switch, as set forth in claim 7, wherein the combinational error detector further comprises:

a second register that stores values to be compared with the fields in the register by the comparison logic.

11. The InfiniBand switch, as set forth in claim 7, wherein the combinational error detector further comprises:

an error flag handler that outputs a indication that the packet should be discarded or truncated when a predetermined error flag is set by the comparison logic.