Method and apparatus for defining vias

• US 6,898,772 B1
• Filed: 08/14/2002
• Issued: 05/24/2005
• Est. Priority Date: 01/22/2002
• Status: Active Grant

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Teig, Steven, Caldwell, Andrew
• Primary Examiner(s): Thompson, A. M.
• Assistant Examiner(s): Dimyan, Magid Y.
• Application Number:
  US10/219,923
• Time in Patent Office: 1,014 Days
• Field of Search: 716/12, 716/13, 716 1- 11, 257/773, 438/617
• US Class Current: 716/122
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Some embodiments of the invention provide a method for identifying locations of potential via between two layers of a design layout. The method identifies on one layer a first non-rectangular polygonal region for containing the via, and identifies on the other layer a second non-rectangular polygonal region for containing the via. It then determines whether an intersection of the first and second regions is sufficiently large to contain a via. If the intersection is sufficiently large, the method identifies the intersection of the two regions as a region for containing a via.

Claims

1. A method of identifying locations of a potential via between two layers of a design layout, the method comprising:

identifying a first non-rectangular polygonal region on one layer for containing the via;

identifying a second non-rectangular polygonal region on the other layer for containing the via;

determining whether an intersection of the first and second regions is sufficiently large to contain a via; and

if the intersection is sufficiently large, identifying the intersection of the first and second regions as a region for containing a via.

2. The method of claim 1 further comprising:

specifying a set of routes for a set of nets in the design layout;

wherein the intersection is identified as a region for containing a via before specifying any route for any net in the design layout.

3. The method of claim 2 further comprising:

before specifying any route for any net in the design layout, decomposing the layout into a plurality of faces;

wherein each of the first and second regions is within a face.

4. The method of claim 1 further comprising:

specifying a set of routes for a set of nets in the design layout;

wherein the intersection is identified as a region for containing a via while specifying a route for a net in the design layout.

5. The method of claim 1 further comprising:

specifying a set of routes for a set of nets in the design layout;

wherein the intersection is identified as a region for containing a via after specifying a route for a net in the design layout.

6. The method of claim 1 further comprising:

decomposing the layout into a plurality of faces, wherein each face has a set of edges and at least one interior space between the edges;

wherein each of the first and second regions is within a space within a face.

7. The method of claim 6, wherein the layout is an integrated circuit (“

IC”

) layout.

8. The method of claim 7, wherein the layout is the layout of a portion of an IC.

9. The method of claim 7, wherein the layout is the layout of a single IC.

10. The method of claim 7, wherein the IC layout includes a plurality of routable elements, wherein decomposing the layout comprises:

specifying a plurality of nodes along boundaries of the routable elements;

defining edges between the nodes.

11. The method of claim 1, wherein the regions have different polygonal shapes.

12. The method of claim 1, wherein at least one of the regions has a non-rectangular polygonal shape.

13. The method of claim 1, wherein the regions are convex polygonal regions.

14. A computer readable medium that stores a computer program that identifies locations of a potential via between two layers of a design layout, the computer program comprising sets of instructions for:

identifying a first non-rectangular polygonal region on one layer for containing the via;

identifying a second non-rectangular polygonal region on the other layer for containing the via,

determining whether an intersection of the first and second regions is sufficiently large to contain a via; and

if the intersection is sufficiently large, identifying the intersection of the first and second regions as a region for containing a via.

15. The computer readable medium of claim 14, wherein the computer program further comprises instructions for specifying a set of routes for a set of nets in the design layout, wherein the intersection is identified as a region for containing a via before specifying any route for any net in the design layout.

16. The computer readable medium of claim 15, wherein the computer program further comprises instructions for decomposing the layout into a plurality of faces before specifying any route for any net in the design layout;

wherein each of the first and second regions is within a face.

17. The computer readable medium of claim 14, wherein the computer program further comprises instructions for specifying a set of routes for a set of nets in the design layout, wherein the intersection is identified as a region for containing a via while specifying a route for a net in the design layout.

18. The computer readable medium of claim 14, wherein the computer program further comprises instructions for specifying a set of routes for a set of nets in the design layout, wherein the intersection is identified as a region for containing a via after specifying a route for a net in the design layout.

19. The computer readable medium of claim 14, wherein the computer program further comprises instructions for decomposing the layout into a plurality of faces, wherein each face has a set of edges and at least one interior space between the edge wherein each of the first and second regions is within a space within a face.

20. The computer readable medium of claim 14, wherein at least one of the regions has a non-rectangular polygonal shape.