Semiconductor device and its manufacture method

• US 6,900,088 B2
• Filed: 02/28/2002
• Issued: 05/31/2005
• Est. Priority Date: 03/09/2001
• Status: Expired due to Term

• Current Assignee: Fujitsu Semiconductor Limited (Fujitsu Limited)
• Original Assignee: Fujitsu Limited
• Inventors: Nakai, Satoshi, Nanjo, Ryota, Sugatani, Shinji
• Primary Examiner(s): Wilczewski, Mary
• Assistant Examiner(s): Thomas, Toniae M.
• Application Number:
  US10/084,367
• Publication Number:
  US 20020127791A1
• Time in Patent Office: 1,188 Days
• Field of Search: 438/210, 438/223, 438/227, 438229-231, 438/238, 438/383, 438/382, 438/275, 438/530, 257/358, 257/379, 257/336, 257/344, 257/350, 257/408
• US Class Current: 438/210
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 21/82385 gate conductors with different shapes, lengths or dimensions

Abstract

First and second gate electrodes are formed on first and second regions of a semiconductor substrate. Second conductivity type impurities are implanted into the second region to form first impurity diffusion regions. Spacer films are formed on the side surfaces of the first and second gate electrodes. Second conductivity type impurities are implanted into the first and second regions to form second impurity diffusion regions. After the spacer films are removed, second conductivity type impurities are implanted into the first region to form third impurity diffusion regions. The third activation process is performed so that the gradient of impurity concentration distribution around the third impurity diffusion region becomes steeper than the gradient of impurity concentration distribution around the first impurity diffusion region.

Claims

1. A method of manufacturing a semiconductor device, comprising the steps of:

(a) preparing a semiconductor substrate having first and second regions of a first conductivity type defined by isolation regions in a principal surface area of the semiconductor substrate;

(b) forming at least a first gate electrode in a partial area of the first region;

(c) implanting impurities of a second conductivity type opposite to said first conductivity type into a surface layer of said second region, and thereafter executing a first activation process to form first impurity diffusion region shallower than said isolation regions, the first impurity diffusion region being directly surrounded by said second region of the first conductivity type, and providing a current path for charge carriers of said second conductivity type;

(d) forming first spacer film on side surface of said first gate electrode;

(e) by using said first gate electrode and said first spacer film as a mask, implanting impurities of said second conductivity type into a surface layer of said first region, and thereafter executing a second activation process to form a second impurity diffusion region;

(f) removing said first spacer film; and

(g) by using said first gate electrode as a mask, implanting impurities of said second conductivity type into a surface layer in said first region, and thereafter executing a third activation process to form third impurity diffusion region, wherein said third activation process is executed so that the gradient of an impurity concentration distribution in a p-n junction formed by the third impurity diffusion region becomes steeper than the gradient of an impurity concentration distribution in a p-n junction formed by said first impurity diffusion region formed by said first activation process.

2. A method of manufacturing a semiconductor device according to claim 1, wherein each of said first to third activation processes includes a thermal treatment at a temperature at least equal to 750°

C.

3. A method of manufacturing a semiconductor device according to claim 1, wherein said third activation process is a laser thermal process.

4. A method of manufacturing a semiconductor device according to claim 1, said step (b) forms first and second gate electrodes in respective partial areas of said first and second active regions, and wherein the gate length of said first gate electrode is shorter than the gate length of said second gate electrode.

5. A method of manufacturing a semiconductor device according to claim 1, wherein said step (c) forms a resistor.

6. A method of manufacturing a semiconductor device according to claim 5, wherein said step (d) also forms a silicidation preventing film on the first impurity diffusion region.

7. A method of manufacturing a semiconductor device according to claim 3, wherein said first and second activating processes are done by rapid thermal annealing.

8. A method of manufacturing a semiconductor device according to claim 1, wherein the gradient of the impurity concentration distribution of the p-n junction formed by the third impurity diffusion region is steeper than the gradient of the impurity concentration distribution of the p-n junction formed by the second impurity diffusion region.