Method of selective removal of SiGe alloys

• US 6,900,094 B2
• Filed: 06/14/2002
• Issued: 05/31/2005
• Est. Priority Date: 06/14/2001
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: AmberWave Systems Corporation
• Inventors: Hammond, Richard, Currie, Matthew
• Primary Examiner(s): LINDSAY JR, WALTER LEE
• Application Number:
  US10/172,542
• Publication Number:
  US 20030013323A1
• Time in Patent Office: 1,082 Days
• Field of Search: 438/238, 438/239, 438/202, 438/439, 438/458, 438/739
• US Class Current: 438/238
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A method is disclosed of forming buried channel devices and surface channel devices on a heterostructure semiconductor substrate. In an embodiment, the method includes the steps of providing a structure including a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate wherein the first oxidation rate is greater than the second oxidation rate, reacting said first layer to form a sacrificial layer, and removing said sacrificial layer to expose said second layer.

Claims

1. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer; and

removing said sacrificial layer to expose said second layer,

wherein the second layer comprises a strained semiconductor.

2. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first aver having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer; and

removing said sacrificial layer to expose said second layer,

wherein the second layer comprises Si.

3. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer; and

removing said sacrificial layer to expose said second layer,

wherein said semiconductor substrate further comprises an insulator layer disposed beneath said second layer.

4. The method as claimed in claim 3, wherein said insulator layer comprises silicon dioxide.

5. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer, wherein said reacting comprises thermal oxidation performed at or below a temperature of approximately 850°

C.; and

removing said sacrificial layer to expose said second layer.

6. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer; and

removing said sacrificial layer to expose said second layer,

wherein said step of reacting said first layer to form a sacrificial layer comprises chemical oxidation.

7. A method of forming a semiconductor substrate, comprising:

providing a structure comprising a first layer having a first oxidation rate disposed over a second layer having a second oxidation rate, wherein the first oxidation rate is greater than the second oxidation rate;

reacting said first layer to form a sacrificial layer; and

removing said sacrificial aver to expose said second layer,

wherein said step of reacting said first layer to form a sacrificial layer is performed on a first region of said first layer and not on a second region of said first layer.

8. The method as claimed in claim 7, wherein said method further comprises forming a surface channel device in said first region.

9. The method as claimed in claim 7, wherein said method further comprises forming a buried channel device in said second region.

10. The method as claimed in claim 7, wherein said method further comprises:

forming a surface channel device in said first region; and

forming a buried channel device in said second region, wherein the channel of said surface channel device and said buried channel device comprises a second device layer.

11. The method as claimed in claim 10, wherein said second layer comprises Si and said first layer comprises SiGe.

12. A method of forming devices on a substrate said method comprising the steps of:

providing a structure comprising a SiGe layer disposed over a strained semiconductor layer; and

selectively removing said SiGe layer in a first region but not in a second region such that a surface channel device may be formed on said first region and a buried channel device may be formed on said second region.

13. A method of forming devices on a substrate, said method comprising the steps of

providing a structure comprising a SiGe layer disposed over a strained semiconductor layer;

oxidizing said SiGe layer to form a SiGe oxide in a first region but not in a second region of said structure;

removing said SiGe oxide; and

forming a surface channel device in said first region and a buried channel device in said second region such that the strained semiconductor layer serves as the channel layer of each device.