Strained silicon MOSFETs having improved thermal dissipation

• US 6,900,143 B1
• Filed: 09/09/2003
• Issued: 05/31/2005
• Est. Priority Date: 09/09/2003
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Pan, James N., Goo, Jung-Suk, Xiang, Qi
• Primary Examiner(s): Pham, Hoai
• Assistant Examiner(s): Ha, Nathan W.
• Application Number:
  US10/658,963
• Time in Patent Office: 630 Days
• Field of Search: 438/149, 438/479, 438/571, 438/572, 257347-353
• US Class Current: 438/752
• CPC Class Codes: H01L 21/28525 the conductive layers comprising semiconducting material H01L21/28518, H01L21/28537 take precedence
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

The thermal conductivity of strained silicon MOSFETs and strained silicon SOI MOSFETs is improved by providing a silicon germanium carbide thermal dissipation layer beneath a silicon germanium layer on which strained silicon is grown. The silicon germanium carbide thermal dissipation layer has a higher thermal conductivity than silicon germanium, thus providing more efficient removal of thermal energy generated in active regions.

Claims

1. A method for the formation of a semiconductor device, comprising:

providing a substrate comprising a silicon layer, a silicon germanium carbide thermal dissipation layer formed on the silicon layer, and a silicon germanium layer formed on the silicon germanium carbide thermal dissipation layer;

growing a layer of strained silicon on the silicon germanium layer; and

forming a MOSFET on the substrate that incorporates the strained silicon in at least a channel region thereof.

2. The method claimed in claim 1, wherein growing the layer of strained silicon is preceded by forming shallow trench isolations in the silicon germanium layer to define an active region of the substrate in which the MOSFET is to be formed.

3. The method claimed in claim 2, wherein the shallow trench isolations comprise an oxide trench liner and a silicon carbide bulk fill material.

4. The method claimed in claim 3, wherein the shallow trench isolations extend through the silicon germanium layer to contact the silicon germanium carbide thermal dissipation layer.

5. The method claimed in claim 1, wherein providing the substrate comprises:

providing a silicon wafer;

growing the silicon germanium carbide thermal dissipation layer on the silicon wafer; and

growing the silicon germanium layer on the silicon germanium carbide thermal dissipation layer.

6. A method for the formation of a semiconductor device, comprising:

providing a substrate comprising a dielectric layer, a silicon germanium carbide thermal dissipation layer formed on the dielectric layer, and a silicon germanium layer formed on the silicon germanium carbide thermal dissipation layer;

growing a layer of strained silicon on the silicon germanium layer; and

forming a MOSFET on the substrate that incorporates the strained silicon in at least a channel region thereof.

7. The method claimed in claim 6, wherein growing the layer of strained silicon is preceded by forming shallow trench isolations in the silicon germanium layer to define an active region of the substrate in which the MOSFET is to be formed.

8. The method claimed in claim 7, wherein the shallow trench isolations comprise an oxide trench liner and a silicon carbide bulk fill material.

9. The method claimed in claim 8, wherein the shallow trench isolations extend through the silicon germanium layer to contact the silicon germanium carbide thermal dissipation layer.

10. The method claimed in claim 6, wherein providing the substrate comprises:

providing a first silicon wafer;

forming the silicon germanium layer on the first silicon wafer;

forming the silicon germanium carbide thermal dissipation layer on the silicon germanium layer;

implanting hydrogen into the silicon germanium layer to form a hydrogen rich region in the silicon germanium layer;

forming a dielectric layer on a second silicon wafer;

bonding the silicon germanium carbide thermal dissipation layer of the first silicon wafer to the dielectric layer of the second silicon wafer and concurrently fracturing the silicon germanium layer in the hydrogen rich region; and

removing first silicon wafer.

11. The method claimed in claim 10 wherein forming the silicon germanium carbide thermal dissipation layer comprises implanting carbon into the silicon germanium layer.

12. The method claimed in claim 10, wherein forming the silicon germanium carbide thermal dissipation layer comprises diffusing carbon into the silicon germanium layer.

13. The method claimed in claim 10, wherein forming the silicon germanium carbide thermal dissipation layer comprises growing the silicon germanium carbide thermal dissipation layer on the silicon germanium layer by chemical vapor deposition using source gases that provide silicon, germanium and carbon precursors.

14. The method claimed in claim 13, wherein the source gases comprise organosilicates.

15. The method claimed in claim 6, wherein providing the substrate comprises:

providing a silicon wafer;

growing the silicon germanium carbide thermal dissipation layer on the silicon wafer;

growing the silicon germanium layer on the silicon germanium carbide thermal dissipation layer;

implanting oxygen into the silicon germanium carbide thermal dissipation layer; and

annealing to form an oxide region in the silicon germanium carbide thermal dissipation layer.