Multi-threshold MIS integrated circuit device and circuit design method thereof
First Claim
1. A multi-threshold MIS integrated circuit device comprising:
- a first macro, including a first internal circuit and a first virtual power supply line connected to the first internal circuit, the first internal circuit including a MIS transistor having a first threshold voltage; and
a first leak-current-shielding MIS transistor cell, having a first gate line connected to a first power control line, having a longitudinal direction coincident with the first gate line, being formed along a side of a macro frame of the first macro, having a second threshold voltage different from the first threshold voltage, having a current path whose one end and another end are connected to a first power supply line and the first virtual power supply line, respectively, wherein the first macro and the first leak-current-shielding MIS transistor cell are formed on a substrate.
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Accused Products
Abstract
On a chip 50A, disposed are macro cell 20A not including a virtual power supply line and a leak-current-shielding MOS transistor of a high threshold voltage, and a leak-current-shielding MOS transistor cell 51 of the high threshold voltage. The transistor cell 51 has a gate line 51G which is coincident with the longitudinal direction of the cell, is disposed along a side of a rectangular cell frame of the macro cell 20A, and has a drain region 51D connected to VDD pads 60 and 61 for external connection, the gate line 51G connected to an I/O cell 73 and a source region 51S connected to a VDD terminal of the macro cell 20A. This VDD terminal functions as a terminal of a virtual power supply line V_VDD.
49 Citations
9 Claims
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1. A multi-threshold MIS integrated circuit device comprising:
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a first macro, including a first internal circuit and a first virtual power supply line connected to the first internal circuit, the first internal circuit including a MIS transistor having a first threshold voltage; and
a first leak-current-shielding MIS transistor cell, having a first gate line connected to a first power control line, having a longitudinal direction coincident with the first gate line, being formed along a side of a macro frame of the first macro, having a second threshold voltage different from the first threshold voltage, having a current path whose one end and another end are connected to a first power supply line and the first virtual power supply line, respectively, wherein the first macro and the first leak-current-shielding MIS transistor cell are formed on a substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification