Electronic assembly with sandwiched capacitors and methods of manufacture

• US 6,900,991 B2
• Filed: 12/03/2001
• Issued: 05/31/2005
• Est. Priority Date: 12/03/2001
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Xie, Hong, Sankman, Robert L., Figueroa, David G., Patel, Priyavadan R., Chung, Chee-Yee, Li, Yuan-Liang, Pinello, William P.
• Primary Examiner(s): Vigushin, John B.
• Application Number:
  US10/006,292
• Publication Number:
  US 20030102555A1
• Time in Patent Office: 1,275 Days
• Field of Search: 361/737, 361/738, 361/760, 361/763, 361/766, 361/780, 361/782, 361/783, 361/794, 361/306.2, 257/691, 257/724, 257/777
• US Class Current: 361/782
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16265 the item being a discrete passive component
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 Aluminum [Al]
• CPC Class Codes: H01L 2924/01029 Copper [Cu]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01047 Silver [Ag]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01082 Lead [Pb]
• CPC Class Codes: H01L 2924/014 Solder alloys
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19103 interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
• CPC Class Codes: H01L 2924/19104 : on the semiconductor or solid-state device, i.e. passive-on-chip
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

To provide high-speed, low inductance capacitive decoupling, an integrated circuit (IC) package includes capacitors positioned within the mounting region between a die and an IC package substrate. A variety of types and sizes of capacitors and substrates can be employed in a variety of geometrical arrangements. In some embodiments, capacitors are sandwiched between die terminals or bumps and the substrate conductors or pads, while in other embodiments, capacitors are positioned between bar-type conductors on the surface of the IC package substrate. Methods of fabrication, as well as application of the package to an electronic assembly and to an electronic system, are also described.

Claims

1. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the conductors include at least a first conductive bar having a height and a width, the height exceeding the width;

a plurality of capacitors distributed substantially throughout the IC mounting region and electrically coupled to the first conductive bar, wherein the plurality of capacitors comprises a plurality of capacitor arrays; and

an IC electrically coupled to the plurality of conductors via the plurality of capacitors.

2. The IC package recited in claim 1, wherein selected ones of the plurality of capacitors are further electrically coupled to a second conductive bar of the plurality of conductors, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

3. The IC package recited in claim 1, wherein each of the plurality of capacitors has a top and a bottom, and wherein selected ones of the plurality of capacitors have at least one terminal on their top and at least one terminal on their bottom.

4. The IC package recited in claim 1, wherein each of the capacitor arrays has a top and a bottom, and wherein selected ones of the capacitor arrays have a plurality of terminals of first and second polarities on their top and a plurality of terminals of first and second polarities on their bottom.

5. The IC package recited in claim 1, wherein selected ones of the plurality of capacitor arrays are interdigitated capacitors.

6. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the conductors include at least a first conductive bar having a height and a width, the height exceeding the width;

at least one capacitor within the IC mounting region and electrically coupled to the first conductive bar, wherein the at least one capacitor is mounted atop the first conductive bar; and

an IC electrically coupled to the plurality of conductors via the at least one capacitor.

7. The IC package recited in claim 6, wherein the at least one capacitor is further electrically coupled to a second conductive bar of the plurality of conductors, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

8. The IC package recited in claim 6, wherein the at least one capacitor has a top and a bottom, and wherein the at least one capacitor has terminals on its top and bottom.

9. The IC package recited in claim 6 and comprising a plurality of capacitors distributed substantially throughout the IC mounting region, each capacitor being in electrical contact with at least one of the conductors.

10. The IC package recited in claim 9, wherein the plurality of capacitors comprises a plurality of sets of capacitors, each set comprising two or more capacitors having ends and being aligned substantially end-to-end.

11. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the plurality of conductors are substantially parallel to one another, and wherein the plurality of conductors include at least a first conductive bar having a height and a width, the height exceeding the width;

a plurality of capacitors within the IC mounting region and electrically coupled to the first conductive bar, wherein the plurality of capacitors comprises a plurality of capacitor arrays; and

an IC electrically coupled to the plurality of conductors via the plurality of capacitors.

12. The IC package recited in claim 11, wherein selected ones of the plurality of capacitors are further electrically coupled to a second conductive bar of the plurality of conductors, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

13. The IC package recited in claim 11, wherein each of the plurality of capacitors has a top and a bottom, and wherein selected ones of the plurality of capacitors have at least one terminal on their top and at least one terminal on their bottom.

14. The IC package recited in claim 11, wherein each of the capacitor arrays has a top and a bottom, and wherein selected ones of the capacitor arrays have a plurality of terminals of first and second polarities on their top and a plurality of terminals of first and second polarities on their bottom.

15. The IC package recited in claim 11, wherein the plurality of capacitor arrays are non-orthogonally mounted atop the plurality of conductors.

16. The IC package recited in claim 15, wherein the conductors are diagonal to the plurality of capacitor arrays.

17. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the plurality of conductors include at least a first conductive bar having a height and a width, the height exceeding the width;

a capacitor array within the IC mounting region and electrically coupled to the first conductive bar; and

an IC electrically coupled to the plurality of conductors via the capacitor array.

18. The IC package recited in claim 17, wherein the capacitor array is further electrically coupled to a second conductive bar of the plurality of conductors, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

19. The IC package recited in claim 18, wherein the at least first and second conductive bars have a gap to accommodate the capacitor array.

20. The IC package recited in claim 17, wherein the capacitor array is non-orthogonally mounted atop the plurality of conductors.

21. The IC package recited in claim 17, wherein the capacitor array has a top and a bottom, and wherein the capacitor array has at least one terminal on its top and at least one terminal on its bottom.

22. The IC package recited in claim 21, wherein the capacitor array has a plurality of terminals of first and second polarities on its top and a plurality of terminals of first and second polarities on its bottom.

23. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the conductors include at least one conductive bar having a height and a width, the height exceeding the width;

a plurality of capacitors within the IC mounting region, wherein the plurality of capacitors are mounted beside and in electrical contact with the at least one conductive bar; and

an IC electrically coupled to the plurality of conductors via the plurality of capacitors.

24. The IC package recited in claim 23, wherein the plurality of conductors comprises at least first and second conductive bars, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

25. The IC package recited in claim 23, wherein selected ones of the plurality of capacitors have a first side and a second side, wherein the first side comprises at least one terminal of first polarity, and wherein the second side comprises at least one terminal of second polarity.

26. The IC package recited in claim 23, wherein selected ones of the plurality of capacitors are mounted beside one of the plurality of conductors.

27. The IC package recited in claim 23, wherein selected ones of the plurality of capacitors are mounted between two of the plurality of conductors.

28. The IC package recited in claim 23, wherein the at least one conductive bar has a length, and wherein at least one of the plurality of capacitors has a length substantially the same as the length of the at least one conductive bar.

29. The IC package recited in claim 23, wherein the plurality of conductors comprises at least first and second conductive bars having a height and a width, the height exceeding the width, wherein the first conductive bar is to couple to a first potential, wherein the second conductive bar is to couple to a second potential, wherein the first and second conductive bars have a length, wherein at least one of the plurality of capacitors has a length substantially the same as the length of the first and second conductive bars and is mounted beside and in electrical contact with the first and second conductive bars, wherein at least another of the plurality of capacitors is a capacitor array, and wherein the at least first and second conductive bars have a gap to accommodate the capacitor array.

30. The IC package recited in claim 29, wherein the capacitor array has a top and a bottom, wherein the capacitor array has at least one terminal on its top and at least one terminal on its bottom, and wherein the at least one terminal on its bottom is coupled to one of the first and second conductive bars.

31. The IC package recited in claim 29, wherein the capacitor array is transverse to the at least one capacitor.

32. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductive bars within an IC mounting region, the conductive bars having a height and a width, the height exceeding the width;

a plurality of capacitors within the IC mounting region, wherein the plurality of capacitors are mounted beside and in electrical contact with selected ones of the conductive bars; and

an IC electrically coupled to the plurality of conductive bars via the plurality of capacitors.

33. The IC package recited in claim 32, wherein selected ones of the plurality of capacitors have a first side and a second side, wherein the first side comprises at least one terminal of first polarity, and wherein the second side comprises at least one terminal of second polarity.

34. The IC package recited in claim 33, wherein the IC comprises a plurality of pads of first and second polarities, wherein the selected ones of the plurality of capacitors have a top and a bottom, wherein at least one terminal on the top is of a first polarity, wherein at least one terminal on the top is of a second polarity, wherein the at least one terminal of first polarity is coupled to at least one corresponding pad of first polarity, and wherein the at least one terminal of second polarity is coupled to at least one corresponding pad of second polarity.

35. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the conductors include at least one conductive bar having a height and a width, the height exceeding the width;

at least one capacitor within the IC mounting region, wherein the at least one capacitor is mounted beside and in electrical contact with the at least one conductive bar; and

an IC electrically coupled to the plurality of conductors.

36. The IC package recited in claim 35, wherein the at least one capacitor is mounted between and electrically coupled to first and second conductive bars.

37. The IC package recited in claim 36, wherein the first conductive bar is to couple to a first potential, and wherein the second conductive bar is to couple to a second potential.

38. The IC package recited in claim 36, wherein the capacitor comprises terminals on two sides, and wherein the terminals are electrically coupled to the first and second conductive bars, respectively.

39. The IC package recited in claim 35, wherein the plurality of conductors are substantially parallel to one another.

40. An integrated circuit (IC) package comprising:

a substrate having a plurality of conductors within an IC mounting region, wherein the plurality of conductors are substantially parallel to one another;

a plurality of capacitors within the IC mounting region and electrically coupled to at least one of the conductors, wherein the plurality of capacitors comprises a plurality of capacitor arrays, and wherein the plurality of capacitor arrays are non-orthogonally mounted atop the plurality of conductors; and

an IC electrically coupled to the plurality of conductors via the plurality of capacitors.

41. The IC package recited in claim 40, wherein the plurality of conductors are substantially parallel to one another.

42. The IC package recited in claim 40, wherein the plurality of conductors are diagonal to the plurality of capacitor arrays.