System and method for high speed packet transmission implementing dual transmit and receive pipelines

• US 6,901,072 B1
• Filed: 05/15/2003
• Issued: 05/31/2005
• Est. Priority Date: 05/15/2003
• Status: Expired due to Term

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Foundry Networks Incorporated (Broadcom, Inc.)
• Inventors: Wong, Yuen Fai
• Primary Examiner(s): Chin, Wellington
• Assistant Examiner(s): PHAM, BRENDA H
• Application Number:
  US10/438,545
• Time in Patent Office: 747 Days
• Field of Search: 370/360, 370/363, 370/365, 370/368, 370/371, 370/374, 370/378, 370/381, 370/389, 370/395.7, 370/395.71, 370/419, 370/428, 370/423, 370/463, 370/474
• US Class Current: 370/389
• CPC Class Codes: H04L 12/4645 Details on frame tagging routing of packets H04L45/00; support for virtual LAN H04L49/354
• CPC Class Codes: H04L 45/745 Address table lookup; Address filtering
• CPC Class Codes: H04L 45/7453 using hashing
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation
• CPC Class Codes: H04L 49/352 Gigabit ethernet switching [GBPS]
• CPC Class Codes: H04L 5/14 Two-way operation using the same type of signal, i.e. duplex
• CPC Class Codes: H04Q 11/0428 Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals

Abstract

The present invention provides systems and methods for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices. According to one embodiment, the system of the present invention comprises a first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces. The system also contemplates a first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and an associated first and second memory structures, the first and second FPGAs are configured to perform initial processing of packets received from the first and second MAC interfaces and to schedule the transmission of packets to the first and second MAC interface for transmission to one or more destination devices. The first and second FPGAs are further operative to dispatch and retrieve packets to and from the first and second memory structures. A third FPGA, coupled to the first and second memory structures and a backplane, is operative to retrieve and dispatch packets to and from the first and second memory structures, compute appropriate destinations for packets and organize packets for transmission. The third FPGA is further operative to receive and dispatch packets to and from the backplane.

Claims

1. A system for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:

first and second media access control (MAC) interfaces to facilitate receipt and transmission of packets over an associated set of physical interfaces;

first and second field programmable gate arrays (FPGA) coupled to the MAC interfaces and associated first and second memory structures, the first and second FPGAs each configured to perform initial processing of packets received from the associated first and second MAC interfaces, respectively, and to schedule the transmission of packets to the first and second MAC interfaces, respectively, for transmission to one or more destination devices, the first and second FPGAs each further operative to dispatch and retrieve packets to and from the first and second memory structures, respectively; and

a third FPGA coupled to the first and second memory structures and a backplane, the third FPGA operative to retrieve and dispatch packets to and from the first and second memory structures and the backplane, compute appropriate destinations for packets and organize packets for transmission.

2. The system of claim 1 wherein the first and second memory structures are quad data rate (QDR) memory modules.

3. The system of claim 1 comprising a plurality of FIFO structures within the first, second and third FPGAs to provide for pipelined processing of data.

4. The system of claim 3 wherein the first and second FPGAs are operative to transfer data in at least 64 bit packets.

5. The system of claim 4 wherein the first and second FPGAs are each configured to perform CAM and PRAM lookups for received packets.

6. The system of claim 5 wherein the first and second FPGAs are each configured to perform multiple CAM and PRAM lookups in parallel.

7. The system of claim 6 wherein at least one of the multiple CAM lookups is a source address lookup and at least one other one of the multiple CAM lookups is a destination address CAM lookup.

8. The system of claim 6 wherein at least one of the multiple PRAM lookups is a sources address PRAM lookup and at least one other one of the multiple PRAM lookups is a destination address PRAM lookup.

9. The system of claim 3 wherein the third FPGA comprises first and second transmit cores, each of the first and second transmit cores operative to provide a receive and transmit pipeline for a given one of the field and second FPGAs, the first and second transmit cores further operative to receive packets from the first and second memory structures and process the packets for dispatch to their intended destinations.

10. The system of claim 9 wherein the first and second transmit cores each comprise a local switching FIFO operative to transfer packets between the first transmit core and the second transmit core.

11. The system of claim 10 wherein the first and second transmit cores each comprise a transmit quality of service module operative to determine an order in which packets received at a given one of the first and second transmit cores from the backplane and the local switching FIFO are transmitted to a given one of the first and second memory structures.

12. The system of claim 3 wherein the third FPGA comprises a backplane transmit sorter operative to organize packets for dispatch to one or more slots on the backplane.

13. The system of claim 12 wherein the backplane transmit sorter implements a number of FIFOs to organize packets prior to transmission to the one or more slots on the backplane.

14. The system of claim 13 wherein the backplane transmit sorter implements a number of FIFOs equal to a number of slots on the backplane.

15. The system of claim 3 wherein the third FPGA comprises a receive FIFO arbiter operative to arbitrate the receipt of data from a plurality of transmit cores for placement in one or more receive FIFOs.

16. The system of claim 3 wherein the third FPGA comprises a backplane transmit grouper operative to modify the size of a data packet for transmission over the backplane.

17. A method for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the method comprising:

receiving packets over a first and second media access control (MAC) interfaces, the first and second MAC interfaces operative to facilitate receipt and transmission of packets over a first and second physical interfaces;

pipelining data bi-directionally through a first and second processors coupled to the first and second MAC interfaces and a first and second memory structures, the first and second processors configured to perform initial processing of received packets to be buffered in the first and second memory structures and scheduling packets for transmission to the MAC interface for transmission to one or more destination devices over the first and second physical interfaces, the first and second processors further operative to dispatch and retrieve packets to and from the first and second memory structures; and

implementing dual bi-directional data pipelines through a third processor coupled to the first and second memory structures and a backplane, the second processor configured to compute an appropriate destination for a packet and organize packets for transmission.

18. The method of claim 17 comprising pipelining data bi-directionally through the first and second memory structures coupled to the first processor and the second processor.

19. The method of claim 17 comprising pipelining through a first, second and third processor wherein each processor comprises a field programmable gate array (FPGA).

20. The method of claim 17 wherein pipelining is accomplished through the use of a plurality of FIFOs in the first, second and third processors.

21. The method of claim 20 wherein pipelining data bi-directionally through the first and second processors comprises performing CAM and PRAM lookups for received packets.

22. The method of claim 21 comprising pipelining CAM and PRAM lookups through the use of a plurality of FIFOs.

23. The method of claim 20 wherein pipelining data bi-directionally through the first and second processors comprises performing multiple CAM and PRAM lookups in parallel.

24. The method of claim 23 wherein performing at least one of the multiple CAM lookups comprises a source address and performing at least one other one of the multiple CAM lookups comprises a destination address.

25. The method of claim 23 wherein performing at least one of the multiple PRAM lookups comprises a source address and performing at least one other one of the multiple PRAM lookups comprises a destination address.

26. The method of claim 17 wherein implementing dual bi-directional data pipelines through the third processor comprises issuing packets on the backplane.

30. The method of claim 17 wherein implementing dual bi-directional data pipelines through a third processor comprises implementing a backplane transmit sorter operative to organize packets for dispatch to one or more slots on the backplane.

31. The system of claim 30 wherein implementing the backplane transmit sorter comprises implementing a number of FIFOs to organize packets prior to transmission to the one or more slots on the backplane.

32. The method of claim 31 wherein implementing the backplane transmit sorter comprises implementing a number of FIFOs equal to a number of slots on the backplane.

33. The system of claim 17 wherein implementing dual bi-directional data pipelines through a third processor comprises implementing a receive FIFO arbiter operative to arbitrate the receipt of data from a plurality of transmit cores for placement in one or more receive FIFOs.

34. The method of claim 17 wherein implementing dual bi-directional data pipelines through a third processor comprises a backplane transmit grouper operative to modify the size of a data packet for transmission over the backplane.

27. The method 17 wherein implementing dual bi-directional data pipelines through a third processor comprises implementing a bi-directional data pipeline in each of a first and second transmit cores, each of the first and second transmit cores operative to provide a receive and transmit pipeline for a given one of the first and second processors, the first and second transmit cores further operative to receive packets from the first and second memory structures and process the packets for dispatch to their intended destinations.

28. The method of claim 27 wherein implementing a bi-directional data pipeline in each of a first and second transmit cores comprise implementing a local switching FIFO operative to transfer packets between the first transmit core and the second transmit core.

29. The method of claim 28 wherein implementing a bi-directional data pipeline in each of a first and second transmit cores comprises implementing a transmit quality of service module in the first and second transmit cores operative to determine the order in which packets received at a given one of the first and second transmit cores from the backplane and the local switching FIFO are transmitted to a given one of the first and second memory structures.

35. A system for providing data transmission speeds at or in excess of 10 gigabits per second between one or more source devices and one or more destination devices, the system comprising:

a first and second transmit and receive data pipelines, the first and second transmit and receive data pipelines used to couple a first and second medial access control (MAC) interfaces to facilitate receipt and transmission packets over a physical interface, and a first and second packet processors configured to perform initial processing of received packets that are buffered in a first and second memory structures; and

a third and fourth transmit and receive data pipelines, the third and fourth transmit and receive data pipelines used to couple a transmission manager to a backplane and the first and second transmit and receive data pipelines, the third and fourth transmit and receive data pipelines configured to receive packets from a backplane, organize the packets for transmission that are buffered in the first and second memory structures and schedule the transmission of packets on the backplane.

36. The system of claim 35 wherein the first, second, third and fourth transmit and receive data pipelines comprise a plurality of FIFO structures to provide for pipelined processing of data.

37. The system of claim 35 wherein the first and second packet processors and the transmission manager are field programmable gate arrays (FPGAs).

38. The system of claim 35 wherein the first and second packet processors and the transmission manager are application specific integrated circuits.

39. The system of claim 35 wherein the first and second memory structures are quad data rate memory structures.