Digital adaptive sensorless commutational drive controller for a brushless DC motor

• US 6,901,212 B2
• Filed: 06/13/2002
• Issued: 05/31/2005
• Est. Priority Date: 06/13/2002
• Status: Expired due to Term

• Current Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Original Assignee: Halliburton Energy Services Incorporated (Halliburton Company)
• Inventors: Masino, James E.
• Primary Examiner(s): Leykin, Rita
• Application Number:
  US10/170,960
• Publication Number:
  US 20030231875A1
• Time in Patent Office: 1,083 Days
• Field of Search: 318/254, 318/138, 318/439, 318/811, 318/799, 388/928.1, 388/928
• US Class Current: 318/400.35
• CPC Class Codes: H02P 6/12 Monitoring commutation; Providing indication of commutation failure
• CPC Class Codes: H02P 6/15 Controlling commutation time
• CPC Class Codes: H02P 6/16 Circuit arrangements for detecting position
• CPC Class Codes: H02P 6/182 using back-emf in windings
• CPC Class Codes: H02P 6/20 Arrangements for starting H02P6/08 takes precedence
• CPC Class Codes: H02P 6/30 Arrangements for controlling the direction of rotation H02P6/22 takes precedence

Abstract

A digitally adaptive controller circuit for commutating a brushless, sensorless, DC motor in either of two directions adapted to receive digital back electromotive force (BEMF) detector signals. The digital circuit is driven by an input clock that is adjustable to configure the motor controller for use with a broad range of DC motors. The circuit includes commutational logic that decodes a current commutational state and a user-definable binary direction input into logic levels for digital control signals for controlling motor drive switches. The circuit also includes a signature analyzer to compare logic levels in the BEMF detector signals with expected logic levels based on an expected rotor position and direction of rotation. The digital circuit commutates the motor if the logic levels in the BEMF detector signals are at the expected logic levels. The digital circuit is compact and simple enough to be deployed onto a single programmable logic device.

Claims

1. A method of providing synchronous commutation to a plurality of phase windings in a brushless, sensorless, direct current (DC) motor comprising:

receiving binary back electromotive force (BEMF) level signals associated with each phase winding, said BEMF level signals indicating whether the voltage level in the associated phase winding is above or below a threshold voltage level;

operating a state machine, said state machine sequentially advancing through a plurality of states, each state being based on the position and motion of the DC motor rotor and each state dictating which of the phase windings in the DC motor are supplied drive power;

detecting changes in the logic level of the BEMF level signals;

counting the amount of time that elapses between adjacent logic level changes in the BEMF level signals;

generating a switch time that is some fraction of the elapsed time between adjacent logic level changes; and

advancing the state machine when the switch time elapses following the most recent logic level change.

2. The method of claim 1, wherein the switch time is substantially equal to half of the elapsed time between adjacent logic level changes.

3. The method of claim 1, further comprising:

detecting a change in the logic level of a BEMF level signal associated with a phase winding that is not driven in a given state.

4. The method of claim 3, further comprising:

counting the amount of time that elapses between adjacent logic level changes in the examined BEMF level signals by counting the number of clock cycles that elapse at a first clock frequency; and

counting to the switch time by counting the same number of elapsed clock cycles at a second clock frequency that is double that of the first clock frequency.

5. The method of claim 4, further comprising:

using a first binary counter clocked at the first clock frequency to count the number of clock cycles that elapse between adjacent logic level changes;

transferring the number of clock cycles counted by the first binary counter to a second binary counter;

using the second binary counter clocked at the second clock frequency to count to the switch time by counting the transferred number of clock cycles; and

generating a switch command when the second binary counter reaches the switch time by counting the transferred number of clock cycles.

6. The method of claim 5, further comprising:

cycling the second binary counter through its maximum counting range if the first binary counter does not detect a logic level change; and

generating a switch command each time the second binary counter cycles through its maximum range.

7. A digital motor controller configured to generate binary output signals to drive a plurality of phase windings in a brushless, sensorless, direct current (DC) motor comprising:

an input means for receiving binary input signals corresponding to each phase winding, each binary input signal indicating whether the back electromotive force (BEMF) voltage level in the associated phase winding is above or below a zero-crossing voltage;

a signature analyzer means for identifying zero crossings in the BEMF levels in the phase windings by generating a zero-crossing signal change that indicates when a binary input signal changes from a first logic level to a second logic level; and

a delay means for counting the amount of time that elapses between the zero crossings and also for generating a switching signal change that is some fraction of the elapsed time between zero crossings;

wherein the switching signal change produces a change in the binary output signals so as to properly commutate the phase windings.

8. The digital motor controller of claim 7, further comprising:

a BEMF multiplexer means for selecting, based on a current logic state, the binary input signal corresponding to a phase winding that is not driven in the current logic state,

wherein the signature analyzer means only identifies logic level changes in the selected binary input signal.

9. The digital motor controller of claim 8, further comprising:

a state machine means for selecting a current logic state from a plurality of logic states; and

a commutational logic means for decoding the current logic state into a logic level for each of the binary output signals;

wherein the switching signal change causes the state machine means to advance to a new current logic state, thereby changing the binary output signals.

10. The digital motor controller of claim 9, further comprising a gate generator means for preventing the signature analyzer means from generating the zero-crossing signal change if the first and second logic levels in the selected binary input signal are opposite in polarity from what is expected for the current logic state.

11. The digital motor controller of claim 10, further comprising:

a first lockout timer means for inhibiting zero crossing detection for a time after a logic state change.

12. The digital motor controller of claim 10, further comprising:

a second lockout timer means for selecting only the first uninhibited zero-crossing signal change in a predetermined amount of time following a logic state change.

13. The digital circuit of claim 12 wherein the digital circuit is deployable onto a single programmable logic device that is operational at temperatures in excess of 150°

C.

14. A digital circuit for commutating a brushless, sensorless, DC motor in either of two directions comprising:

an input circuit adapted to receive digital back electromotive force (BEMF) detector signals, each signal indicating whether the voltage level in an associated phase winding in the DC motor is above a voltage threshold;

a commutational logic circuit adapted to generate digital control signals for controlling DC motor drive switches; and

a signature analyzer circuit configured to compare logic levels in the BEMF detector signals with expected logic levels based on an expected rotor position,

wherein the digital circuit commutates the digital control signals if the logic levels in the BEMF detector signals are at the expected logic levels.

15. The digital circuit of claim 14 wherein the digital circuit is deployable onto a single programmable logic device.

16. The digital circuit of claim 15 wherein the programmable logic device is a semiconductor on insulator device operational at temperatures in excess of 150°

C.

17. The digital circuit of claim 16 wherein the commutational logic further comprises:

a state machine configured cycle sequentially through one of a plurality of commutational states,

wherein the commutational logic decodes each commutational state and a user-definable binary direction input into logic levels for each of the digital control signals.

18. The digital circuit of claim 17 comprising six commutational states.

19. The digital circuit of claim 17 comprising six digital control signals for controlling six DC motor drive switches configured to drive three phase windings in the DC motor.

20. The digital circuit of claim 19 wherein in each commutational state, the digital control signals are configured to couple a first phase winding to a high voltage, a second phase winding to a low voltage, and the third phase winding to neither the high nor the low voltage.

21. The digital circuit of claim 20 further comprising:

a BEMF multiplexer to select and transmit the digital BEMF detector signal from the third phase winding to a signature analyzer,

wherein the signature analyzer generates a zero crossing pulse when the digital BEMF detector signal transitions from a first expected logic level to a second expected logic level.

22. The digital circuit of claim 21 further comprising an adaptive delay circuit configured to:

a) count, at a first clock frequency, the number of clock cycles that elapse between adjacent zero crossing pulses, and

b) count, at a second clock frequency double that of the first clock frequency, the same number of elapsed clock cycles determined from step a),

wherein when the counting in step b) is complete, the adaptive delay circuit generates a switching pulse, to advance the commutational state machine.

23. The digital circuit of claim 22 wherein if the adaptive delay circuit does not sense a zero crossing in a predetermined period of time, the adaptive delay circuit generates a switching pulse to advance the commutational state machine.

24. The digital circuit of claim 23 wherein the clock frequencies are adjustable.

25. A method of controlling the operation of a three-phase brushless DC motor comprising:

activating a current logic state in a state machine that is configured to cycle through a sequence of logic states, each logic state corresponding to a rotor position and travel;

transmitting digital drive signals that control the position of switches that, for each logic state, are adapted to push or pull two of the three windings to a voltage source;

pulling a first phase winding in the DC motor to a high voltage source;

pushing a second phase winding in the DC motor to a low voltage source;

detecting rising and falling voltage threshold crossing directions in back EMF levels of the third, undriven phase winding in the DC motor; and

comparing the rising or falling direction of a detected voltage threshold crossing with an anticipated rising or falling direction for the voltage threshold crossing,

wherein if the direction of the detected voltage threshold crossing matches the anticipated direction for the voltage threshold crossing, generating a zero-crossing command, thereby initiating a logic state change in the state machine.

26. The method of claim 25, further comprising:

selectively detecting the rising and falling voltage threshold crossing directions in back EMF levels in only the third, undriven phase winding.

27. The method of claim 26, further comprising:

counting the time that elapses between zero-crossing commands;

calculating a lag time by dividing this elapsed time approximately in half;

adding the lag time to the point at which a most recently detected zero crossing command was issued;

initiating a state change in the state machine at the end of the lag time.

28. The method of claim 27, wherein if no zero crossing commands are detected in a pre-configured amount of time, initiating a state change in the state machine at the end of the pre-configured amount of time.

29. A digital circuit for commutating a brushless, sensorless, DC motor comprising:

an input circuit adapted to receive digital back electromotive force (BEMF) detector signals, each signal indicating whether the voltage level in an associated phase winding in the DC motor is above a voltage threshold;

a commutational logic circuit adapted to generate digital control signals for controlling power delivery to individual DC motor windings; and

a signature analyzer circuit configured to compare logic levels in the BEMF detector signals with expected logic levels based on an expected rotor position,

wherein the digital circuit commutates the digital control signals if the logic levels in the BEMF detector signals are at the expected logic levels and wherein the digital circuit is deployable onto a programmable logic device that is disposed on a semiconductor on insulator device.

30. The digital circuit of claim 29 wherein the programmable logic device is operational at temperatures above military grade semiconductor device limits of 130°

C.

31. The digital circuit of claim 30 wherein the commutational logic further comprises:

a state machine configured to cycle sequentially through one of a plurality of commutational states,

wherein the commutational logic decodes each commutational state and a user-definable binary direction input into logic levels for each of the digital control signals.

32. The digital circuit of claim 31 comprising six commutational states.

33. The digital circuit of claim 31 comprising six digital control signals for controlling six DC motor drive switches configured to drive three phase windings in the DC motor.

34. The digital circuit of claim 33 wherein in each commutational state, the digital control signals are configured to couple a first phase winding to a high voltage, a second phase winding to a low voltage, and the third phase winding to neither the high nor the low voltage.

35. The digital circuit of claim 34 further comprising:

a BEMF multiplexer to select and transmit the digital BEMF detector signal from the third phase winding to a signature analyzer,

wherein the signature analyzer generates a zero crossing pulse when the digital BEMF detector signal transitions from a first expected logic level to a second expected logic level.

36. The digital circuit of claim 35 further comprising an adaptive delay circuit configured to:

a) count, at a first clock frequency, the number of clock cycles that elapse between adjacent zero crossing pulses, and

b) count, at a second clock frequency double that of the first clock frequency,

the same number of elapsed clock cycles determined from step a),

wherein when the counting in step b) is complete, the adaptive delay circuit generates a switching pulse to advance the commutational state machine.

37. The digital circuit of claim 36 wherein if the adaptive delay circuit does not sense a zero crossing in a predetermined period of time, the adaptive delay circuit generates a switching pulse to advance the commutational state machine.

38. The digital circuit of claim 37 wherein the clock frequencies are adjustable.

39. A digital motor controller to commutate a brushless, sensorless, DC motor comprising:

an input circuit adapted to receive digital back electromotive force (BEMF) detector signals, each signal indicating whether the voltage level in an associated phase winding in the DC motor is above a voltage threshold;

a commutational logic circuit adapted to generate digital control signals for controlling power delivery to individual DC motor windings; and

a signature analyzer circuit configured to compare logic levels in the BEMF detector signals with expected logic levels based on an expected rotor position,

wherein the motor controller is driven by a single input clock and said motor controller is configurable for use with different sensorless, brushless DC motors by adjusting the frequency of the input clock.

40. The digital circuit of claim 39 wherein the digital circuit commutates the digital control signals if the logic levels in the BEMF detector signals are at the expected logic levels and wherein the digital circuit is deployable onto a programmable logic device that is disposed on a semiconductor on insulator device.

41. The digital circuit of claim 40 wherein the commutational logic further comprises:

a state machine configured to cycle sequentially through one of a plurality of commutational states,

wherein the commutational logic decodes each commutational state and a user-definable binary direction input into logic levels for each of the digital control signals.

42. The digital circuit of claim 41 further comprising:

a BEMF multiplexer to select and transmit the digital BEMF detector signal from an undriven phase winding to a signature analyzer,

wherein the signature analyzer generates a zero crossing pulse when the digital BEMF detector signal transitions from a first expected logic level to a second expected logic level.

43. The digital circuit of claim 42 further comprising an adaptive delay circuit configured to:

a) count, at the input clock frequency, the number of clock cycles that elapse between adjacent zero crossing pulses, and

b) count, at a second, faster clock frequency, the same number of elapsed clock cycles determined from step a),

wherein when the counting in step b) is complete, the adaptive delay circuit generates a switching pulse to advance the commutational state machine.

44. The digital circuit of claim 43 wherein the second clock frequency is double that of the input clock frequency.

45. The digital circuit of claim 43 wherein if the adaptive delay circuit does not sense a zero crossing in a predetermined period of time, the adaptive delay circuit generates a switching pulse to advance the commutational state machine.

46. The digital circuit of claim 43, further comprising:

a first lockout timer for delaying the time after a commutational state change at which the signature analyzer begins comparing logic levels in the BEMF detector signals with expected logic levels.

47. The digital circuit of claim 46, further comprising:

a second lockout timer to allow the adaptive delay circuit to receive only the first zero-crossing signal change in a predetermined amount of time following a commutational state change.

48. The digital circuit of claim 39, wherein if the logic levels in the BEMF detector signals are at the expected logic levels the digital circuit commutates the digital control signals synchronously with a zero crossing, and wherein if the logic levels are not at the expected logic levels, the digital circuit asynchronously commutates the digital control signals.

49. The digital circuit of claim 39, wherein the frequency of the input clock is the only parameter that must be adjusted to configure the motor controller for operation with different sensorless, brushless DC motors.

50. The digital circuit of claim 39, wherein the frequency of the input clock is a function of one or more of the following independent variables:

the upper rotational speed limit of the motor, and the number of magnetic pole pairs in the motor.

51. The digital circuit of claim 39, wherein the frequency of the input clock is a function of principally the following independent variables:

the upper rotational speed limit of the motor, and the number of magnetic pole pairs in the motor.