MULTILAYER BOARD IN WHICH WIRING OF SIGNAL LINE THAT REQUIRES TAMPER-RESISTANCE IS COVERED BY COMPONENT OR FOIL, DESIGN APPARATUS, METHOD, AND PROGRAM FOR THE MULTILAYER BOARD, AND MEDIUM RECORDING THE PROGRAM

• US 6,901,343 B2
• Filed: 12/20/2001
• Issued: 05/31/2005
• Est. Priority Date: 01/10/2001
• Status: Expired due to Term

• Current Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Matsushita Electric Industrial Company Limited (Panasonic Holdings Corporation)
• Inventors: Takahashi, Eiji, Shibata, Osamu, Saito, Yoshiyuki, Nakayama, Takeshi, Tanimoto, Shinichi, Fukumoto, Yukihiro
• Primary Examiner(s): Tsai, Carol S. W.
• Application Number:
  US10/029,571
• Publication Number:
  US 20030033108A1
• Time in Patent Office: 1,258 Days
• Field of Search: 257/202, 257207-212, 257/773, 257/774, 257/776, 257/686, 257/93, 257/700, 257/734, 361760-767, 361/791, 361/792, 361/794, 361/795, 702/57, 702/60, 702/62, 702/64, 702/65, 702/119, 702/133, 702FOR 103-104, 702/FOR.106, 702/FOR.111, 702/FOR.157, 702/FOR.155, 713/194, 713/200, 174/52.1, 174/52.4, 174/262, 174/260, 174/261, 174/255, 174/264, 174/265, 174/266, 439/69, 439/65, 716 1- 18
• US Class Current: 702/119
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H05K 1/0275 Security details, e.g. tampering prevention or detection
• CPC Class Codes: H05K 1/0298 Multilayer circuits
• CPC Class Codes: H05K 1/114 Pad being close to via, but not surrounding the via
• CPC Class Codes: H05K 2201/09627 Special connections between adjacent vias, not for grounding vias redundant conductors or connections H05K2201/0979
• CPC Class Codes: H05K 2201/09772 Conductors directly under a component but not electrically connected to the component cooling of mounted components by printed thermal vias H05K1/0206
• CPC Class Codes: H05K 2201/10151 Sensor

Abstract

A signal line, being in a six-layer board and connecting terminal 102 of component 101 with terminal 115 of component 114, requires tamper-resistance. The signal line is composed of foil 103 on an outside layer, a via 104, foil 111 on the third layer, via 105, foil 112 on the fourth layer, via 106, and foil 113 on the sixth layer. Portions of the signal line that exist on outside layers are all hidden under circuit components. Foil 103 and an end of via 104 are placed under component 101 on first layer 116, an end of via 105 is placed under component 107 on layer 116, an end of via 106 is placed under component 108 on layer 116, the other end of via 104 is placed under component 109 on sixth layer 121, the other end of via 105 is placed under component 110 on layer 121, and foil 113 and the other end of via 106 are placed under component 114 on layer 121.

Claims

1. A multilayer board on whose outside layer, one or more circuit components are mounted, the multilayer board comprising:

a signal line requiring tamper-resistance, the signal line being connected to a predetermined component among the one or more circuit components and including;

(a) a conductive and (b) a conductive via that passes through layers of the multilayer board, wherein

the conductive trace and an end of the conductive via existing on the outside layer of the multilayer board are placed only under the predetermined component, and not on the other area of the outside layer.

2. The multilayer board of claim 1, wherein

the signal line further includes a conductive trace on an inner layer that is sandwiched between sheets of foil and/or circuit components placed on layers above and below the inner layer so that the sheets of foil and/or circuit components hide the conductive trace on the inner layer when viewed from above or below.

3. The multilayer board of claim 2, wherein

the sheets of foil placed on the layers that are outside the inner layer are connected to either a ground or a power source.

4. The multilayer board of claim 3, wherein

the conductive trace on the outside layer is further covered by a circuit component on another outside layer when viewed from above or below.

5. The multilayer board of claim 2, wherein

the signal line requiring tamper-resistance is either a signal line that is input to an encryption unit or a signal line that is output from a decryption unit.

6. A multilayer board on whose outside layer, one or more circuit components are mounted, the multilayer board comprising:

a certain signal line that is connected to a predetermined component among the one or more circuit components and includes (a) a conductive trace and (b) a conductive via that passes through layers of the multilayer board, wherein

the conductive trace and an end of the conductive via existing on the outside layer of the multilayer board are placed only under the predetermined component, and not on the other area of the outside layer,

the certain signal line further includes a conductive trace on an inner layer of the multilayer board, the conductive trace being sandwiched between sheets of foil and/or circuit components placed on layers above and below the inner layer so that the sheets of foil and/or the predetermined component hide the conductive trace on the inner layer when viewed from above or below, and

the certain signal line is either a data line or an address line.

7. A tamper-resistant multilayer board for transfer of pixel data to be encrypted comprising:

a board member having a plurality of layers and one or more components mounted thereon;

a reception/decryption unit mounted on the board member;

an output interface unit mounted on the board member and operatively connected to the reception/decryption unit; and

a conductive path operatively designed for interconnecting the reception/decryption unit and the output interface unit and positioned adjacent an interior layer surface for a first portion of the conductive path and positioned only under the reception/decryption unit and/or the output interface unit for a second portion of the conductive path on an outside layer of the multilayer board to prevent direct access to the second portion of the conductive path from the exterior of the board member.