Multiprocessor machine and cache control method for providing higher priority to shared cache that is accessed by multiprocessors

• US 6,901,450 B1
• Filed: 09/22/2000
• Issued: 05/31/2005
• Est. Priority Date: 09/22/2000
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Shimada, Kentaro
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US09/667,716
• Time in Patent Office: 1,712 Days
• Field of Search: 709/232, 709/238, 711/133, 711/144, 711/145, 711/122, 711/130, 711/135, 711/136, 711/141, 711/118, 711/121, 711/124
• US Class Current: 709/232
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/127 using additional replacement algorithms

Abstract

In multiprocessor machines and chip multiprocessor systems in particular, the object of the present invention is to reduce data communication between the LSI chip and external components and to avoid restrictions in communication volume resulting from the LSI pin count. Sets in tag and data blocks of a shared cache include a shared bit S. When data is replaced for a cache miss, the contents of the shared bit S are checked and the side with the shared bit S set to 0 in the tag and data block is selected for data replacement. This allows data shared by a plurality of processors to be left in the shared cache, and the data transfer between the shared cache and the main memory can be reduced.

Claims

1. A multiprocessor machine comprising:

a plurality of processors;

a first cache shared by said plurality of processors; and

a first controller providing control so that data accessed by at least two processors out of said plurality of processors is given higher priority in being saved to said first cache compared to data accessed by only one of said plurality of processors;

second caches associated with each of said plurality of processors; and

a second controller providing control so that, when data stored in a second cache is accessed by a processor other than a processor associated with said second cache, said data is not stored in said second cache with a higher priority compared to data accessed only by said processor associated with said second cache.

2. A multiprocessor machine as described in claim 1 wherein said plurality of processors and said first cache and said controller and said second cache and said second controller are integrated on a single LSI.

3. A multiprocessor machine as described in claim 1 wherein said second controller includes second selecting means which, if storing new data to said second cache and there is an area in said second cache containing data accessed by a processor other than a processor associated with said second cache, selects said area in said second cache over an area containing data accessed by only said processor associated with said second cache.

4. A multiprocessor machine comprising:

a plurality of processors;

a first cache shared by said plurality of processors; and

a first controller providing control so that data accessed by at least two processors out of said plurality of processors is given higher Priority in being saved to said first cache compared to data accessed by only one of said plurality of processors,

wherein said first controller includes first selecting means which, if storing new data to said first cache and there is an area in said first cache containing data not accessed by at least two processors of aid plurality of processors, selects said area in said first cache over an area containing data accessed by at least two processors of said plurality of processors.

5. A method for controlling cache comprising:

a first step evaluating whether data stored in a cache shared by a plurality of processors is accessed by at least two processors from said plurality of processors;

a second step selecting an area determined by said first step to not be accessed by at least two processors when storing new data to said cache;

a third step selecting an area in said cache if no area can be selected in said second step; and

a fourth step storing said new data in said cache area selected by either said second step or said third step.

6. A method for controlling cache as described in claim 5 wherein said third step selects an area containing data with the lowest number of accessing processors.

7. A processor system comprising:

a plurality of processors;

a cache memory accessible by at least two processors of said plurality of processors;

a first bus connecting said plurality of processors and said cache memory;

a main storage memory exchanging data with said cache memory;

a second bus connecting said cache memory and said main storage memory;

a sharing evaluation module evaluating whether data stored in said cache memory is accessed by at least two processors and adding attributes to said data; and

a replacement controller selecting data in said cache memory determined to not be accessed by at least two processors based on said attributes over data determined to be accessed by at least two processors, and replacing data in said main storage memory with said selected data.

8. A processor system as described in claim 7 wherein said cache memory includes a plurality of sets, said sets containing information indicating whether data in said sets is use by a plurality of processors.

9. A processor system as described in claim 8 wherein said sets include information indicating validity of data and information indicating whether data was rewritten.

10. A processor system as described in claim 9 wherein said sets include an identifier of a processor that last accessed said data.

11. A processor system as described in claim 10 wherein said replacement controller selects an area of said cache memory to replace data in said main storage memory based on said information indicating whether data in said set is use by a plurality of processors, said information indicating validity of data, and said information indicating whether data was rewritten.