Hardware assisted ATA command queuing
First Claim
1. An apparatus, comprising:
- a storage device host controller to provide communication with a storage device over a serial interconnect;
a queue to store a plurality of storage device command programming entries;
a direct memory access unit coupled to the storage device host controller and the queue, where the storage device host controller uses the direct memory access unit to read from a system memory to retrieve information to be stored in the queue;
and further wherein the storage device host controller is operable to deliver programming information to the storage device that corresponds to a first one of the plurality of storage device command programming entries, wherein each of the plurality of storage device command programming entries includes an indication as to whether the entry is valid.
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Accused Products
Abstract
One embodiment involves having a processor writing disk drive command information for a number of data transactions to cacheable system memory. The processor then performs a single write transaction to a disk drive host controller. The disk drive host controller then causes a DMA transfer to occur which reads the command information located in system memory and stores the command information in a queue. Once the host controller has the command information, it programs the disk drive with information corresponding to a queue entry over a serial interconnect. The disk drive signals an interrupt after it processes the command information. The disk drive host controller does not forward the interrupt to the processor, but services the interrupt itself. The disk drive host controller reads from the disk drive to determine the disk drive status. The disk drive can signal that it is ready to execute the programmed command, or it can signal that it is not ready to perform the programmed command but is ready to receive additional command programming information corresponding to another queue entry, or it may signal that it is ready to execute a previously programmed command. The disk drive host controller then performs the required operations using the information stored in the queue without involving the processor. Because the processor is only involved in setting up a command block in system memory and in signaling the disk drive host controller that the command block is ready for reading, the processor is freed up to perform other tasks and overall system performance is improved.
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Citations
24 Claims
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1. An apparatus, comprising:
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a storage device host controller to provide communication with a storage device over a serial interconnect;
a queue to store a plurality of storage device command programming entries;
a direct memory access unit coupled to the storage device host controller and the queue, where the storage device host controller uses the direct memory access unit to read from a system memory to retrieve information to be stored in the queue;
and further wherein the storage device host controller is operable to deliver programming information to the storage device that corresponds to a first one of the plurality of storage device command programming entries, wherein each of the plurality of storage device command programming entries includes an indication as to whether the entry is valid. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A method, comprising:
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storing a plurality of storage device command programming entries in a queue within a storage device host controller, wherein storing the plurality of storage device command programming entries in the queue includes performing a direct memory access transaction to retrieve command programming entry information from a system memory and storing the retrieve command programming entry information in the queue;
delivering command programming information corresponding to a first one of the plurality or storage device command programming entries to a storage device;
receiving an interrupt at the storage device host controller from a storage device;
the storage device host controller performing a read transaction from the storage device to determine that the storage device is not ready to perform a data transaction corresponding to the first one of the plurality of storage device command programming entries but is ready to receive command programming information corresponding to a second one of the plurality of storage device command programming entries. - View Dependent Claims (11, 12, 13, 14, 15)
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16. A system, comprising:
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a processor;
a memory controller hub coupled to the processor;
a system memory coupled to the memory controller hub;
a storage device; and
an input/output controller hub including a storage device host controller to provide communication with the storage device over a serial interconnect and to deliver programming information to the storage device that corresponds to a first one of the plurality of storage device command programming entries, each of the plurality of storage device command programming entries including an indication as to whether the entry is valid, and a direct memory access unit coupled to the storage device host controller and the queue, wherein the storage device host controller uses the direct memory access unit to read from the system memory to retrieve information to be stored in the queue;
a queue to store a plurality of storage device command programming entries. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23, 24)
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Specification
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- Resources
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Current AssigneeIntel Corporation
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Original AssigneeIntel Corporation
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InventorsBennett, Joseph A.
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Primary Examiner(s)Elamin, A.
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Application NumberUS10/334,840Publication NumberTime in Patent Office882 DaysField of Search710/22, 710/71, 710/106, 710/305US Class Current710/22CPC Class CodesG06F 13/385 for adaptation of a particu...G06F 3/0601 Interfaces specially adapte...G06F 3/0673 Single storage device
