Embedded carrier for an integrated circuit chip

• US 6,903,458 B1
• Filed: 06/20/2002
• Issued: 06/07/2005
• Est. Priority Date: 06/20/2002
• Status: Expired due to Fees

• Current Assignee: Richard J. Nathan
• Original Assignee: Richard J. Nathan
• Inventors: Nathan, Richard J.
• Primary Examiner(s): Whitehead, Jr., Carl
• Assistant Examiner(s): Smoot, Stephen W.
• Application Number:
  US10/177,841
• Time in Patent Office: 1,083 Days
• Field of Search: 257/702, 257/737, 257/772, 257/777, 257/778, 257/787, 438/108, 438/613, 361/768, 361/783
• US Class Current: 257/737
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16146 the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/24227 the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/73209 Bump and HDI connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 23/49833 the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA

Abstract

A carrier for an integrated chip is embedded into a substrate, so that stresses due to thermal expansion are uniformly distributed over an interface between the substrate and the carrier (hereinafter “embedded carrier”). Such an embedded carrier may be formed of a material having a coefficient of thermal expansion similar or identical to the coefficient of thermal expansion of an integrated circuit chip to be mounted thereon, so as to eliminate stresses (due to thermal expansion) at joints between the carrier and the integrated circuit chip. The just-described joints may be formed by any method well known in the art, e.g. flip-chip bonding. Such packaging of one or more integrated circuit chip(s) eliminates reliability issues associated with conventional flip chip bonded components, which are caused by, for example, concentration of stresses in conventional solder ball interconnections between a chip and a substrate.

Claims

1. An electronic component comprising:

a substrate having a top surface and a bottom surface opposite the top surface;

a structure embedded within the substrate, the structure comprising a plurality of conductive pads facing up (hereinafter “

face-up pads”

);

wherein the structure and the substrate are included in a monolithic integrated structure such that;

at least a portion of a bottom surface of the structure is in contact with the substrate to form an interface between the structure and the substrate; and

the structure has a top surface substantially coplanar with the top surface of the substrate;

an integrated circuit chip mounted face down on the structure, the integrated circuit chip comprising another plurality of conductive pads (hereinafter “

face-down pads”

) opposite to the face-up pads; and

a plurality of solder joints connecting the face-up pads to the face-down pads.

2. The electronic component of claim 1 further comprising:

underfill located between the structure and the integrated circuit chip;

wherein the underfill is flexible enough to permit displacement between the structure and the integrated circuit chip due to thermal expansion.

3. The electronic component of claim 1 wherein:

the integrated circuit chip comprises a semiconductor material; and

the structure comprises said semiconductor material.

4. The electronic component of claim 1 wherein:

the integrated circuit chip comprises a first semiconductor material; and

the structure comprises a second semiconductor material.

5. The electronic component of claim 1 wherein:

in addition to said face-up pads (hereinafter “

first face-up pads”

), the structure comprises another plurality of conductive pads (hereinafter “

second face-up pads”

), and said integrated circuit chip is hereinafter “

first integrated circuit chip”

; and

the electronic component further comprises another integrated circuit chip (hereinafter “

second integrated circuit chip”

) also mounted face down on said structure, the second integrated circuit chip comprising yet another plurality of conductive pads (hereinafter “

second face-down pads”

) opposite to the second face-up pads; and

another plurality of solder joints connecting the second face-up pads to the second face-down pads.

6. The electronic component of claim 5 wherein:

the structure comprises a conductive link between one of the first face-up pads and one of the second face-up pads.

7. The electronic component of claim 5 wherein each of the first face-up pads and the second face-up pads comprise at least one of nickel and gold.

8. The electronic component of claim 1 wherein:

the integrated circuit chip is hereinafter “

first integrated circuit chip”

; and

the structure comprises a second integrated circuit chip.

9. The electronic component of claim 1 where the embedded structure comprises at least one active device.

10. The electronic component of claim 9 where the active device is a power transistor.

11. The electronic component of claim 1 where the embedded structure comprises at least one passive device.

12. The electronic component of claim 11 where the passive device is a capacitor.

13. The electronic component of claim 11 where the passive device is a resistor.

14. The electronic component of claim 1 where the embedded structure comprises at least one passive device and at least one active device.

15. The electronic component of claim 1 where the substrate comprises a ceramic material.

16. An electronic component comprising:

a substrate;

a structure embedded within the substrate, the structure comprising a plurality of conductive pads facing up (hereinafter “

face-up pads”

);

an integrated circuit chip mounted face down on the structure, the integrated circuit chip comprising another plurality of conductive pads (hereinafter “

face-down pads”

) opposite to the face-up pads; and

a plurality of solder joints connecting the face-up pads to the face-down pads;

wherein the substrate comprises a plastic including fibers selected from a group consisting of glass, fiber glass and aramid materials; and

the coefficient of thermal expansion of the structure is between the coefficient of thermal expansion of the integrated circuit chip and the coefficient of thermal expansion of the substrate.

17. The electronic component of claim 16 where the embedded structure comprises at least one active device.

18. The electronic component of claim 17 where the active device is a power transistor.

19. The electronic component of claim 16 where the embedded structure comprises at least one passive device.

20. The electronic component of claim 19 where the passive device is a capacitor.

21. The electronic component of claim 19 where the passive device is a resistor.

22. The electronic component of claim 16 where the embedded structure comprises at least one passive and at least one active device.

23. The electronic component of claim 16 where the substrate comprises a ceramic material.

24. An electronic component comprising:

a substrate having a top surface and a bottom surface opposite the top surface;

a structure embedded within the substrate, the structure comprising a plurality of conductive pads facing up (hereinafter “

face-up pads”

);

an integrated circuit chip mounted face down on the structure, the integrated circuit chip comprising another plurality of conductive pads (hereinafter “

face-down pads”

) opposite to the face-up pads; and

a plurality of solder joints connecting the face up pads to the face-down pads;

wherein the structure has a top surface substantially coplanar with the top surface of the substrate and the structure has a plurality of lands at a periphery thereof; and

the electronic component further comprises a lay of conductive material formed over said top surface of said structure and said top surface of said substrate, the layer being patterned to form an electrically conductive interconnect structure interconnecting the lands to another plurality of lands on the substrate.

25. The electronic component of claim 24 where the embedded structure comprises at least one active device.

26. The electronic component of claim 25 where the active device is a power transistor.

27. The electronic component of claim 24 where the embedded structure comprises at least one passive device.

28. The electronic component of claim 27 where the passive device is a capacitor.

29. The electronic component of claim 27 where the passive device is a resistor.

30. The electronic component of claim 24 where the embedded structure comprises at least one passive device and at least one active device.

31. The electronic component of claim 24 where the substrate comprises a ceramic material.

32. An electronic component comprising:

a substrate

a structure embedded within the substrate, the structure comprising a plurality of conductive pads facing up (hereinafter “

face-up pads”

);

an integrated circuit chip mounted face down on the structure, the integrated circuit chip comprising another plurality of conductive pads (hereinafter “

face-down pads”

) opposite to the face-up pads; and

a plurality of solder joints connecting the face-up pads to the face-down pads;

wherein the structure embedded within the substrate comprises a plurality of vias, each via being connected to one of the face-up pads.

33. The electronic component of claim 32 wherein:

the face-up pads are hereinafter “

first face-up pades” and

the face-down pads are hereinafter “

first face down pads”

; and

the structure comprises a plurality of second face-down pads arranged at locations identical to the plurality of first face-up pads, and connected thereto by the plurality of vias.

34. The electronic component of claim 32 where the embedded structure comprises at least one active device.

35. The electronic component of claim 34 where the active device is a power transistor.

36. Th electronic component of claim 32 where the embedded structure comprises at least one passive device.

37. The electronic component of claim 36 where the passive device is a capacitor.

38. The electronic component of claim 36 where the passive device is a resistor.

39.The electronic component of claim 32 where the embedded structure comprises at least one passive device and at least one active device.

39. The electronic component of claim 32 where the substrate comprises a ceramic material.

40. An electronic component comprising:

a substrate;

a structure embedded within the substrate, the structure comprising a plurality of conductive pads facing up (hereinafter “

face-up pads”

);

“

an integrated circuit chip mounted face down on the structure, the integrated circuit chip comprising another plurality of conductive pads (hereinafter “

face-down pads”

) opposite to the face-up pads; and

a plurality of solder joints connecting the face-up pads to the face-down pads;

wherein the face-up pads are hereinafter “

first face-up pads” and

the face-down pads are hereinafter “

first face-down pads”

; and

the structure comprises a plurality of second face-down pads arranged at locations spread out from the plurality of first face-up pads.

41. The electronic component of claim 41 where the embedded structure comprises at least one active device.

43. The electronic component of claim 41 where the embedded structure comprises at least one passive device.

46. The electronic component of claim 41 where th mbedded structure comprises at least one passive device and at least one active device.

47. The electronic component of claim 41 where the substrate comprises a ceramic material.

42. The electronic component of claim 42 where the active device is a power transistor.

44. The electronic component of claim 44 where the passive device is a capacitor.

45. The electronic component of claim 44 where the passive device is a resistor.

48. A structure comprising:

a substrate comprising a plurality of lands (hereinafter “

first lands”

); and

a carrier embedded within the substrate, the carrier comprising another plurality of lands (hereinafter “

second lands”

) electrically connected to the first lands, the carrier further comprising a plurality of conductive pads, the pads being arranged in a two of traces that electrically connect each of the pads to one of the second lands;

wherein;

the first lands are formed on a surface of the substrate;

the second lands are formed on a surface of the carrier, said surface of the carrier is substantially coplanar with said surface of the substrate; and

the carrier comprises a plurality of traces formed on said surfaces and connecting the first lands to the second lands.

49. The structure of claim 49 wherein:

the first lands are formed on a top surface of the substrate;

the second lands are formed on a top surface of the carrier, and the pads are also formed on said top surface of the carrier, the second lands being formed at a periphery of the carrier.

50. The structure of claim 49 wherein:

the first lands are formed on a bottom surface of the substrate;

the second lands are formed on a bottom surface of the carrier, and the second lands are arranged in a two dimensional array on said bottom surface of the carrier, the pads are formed on a top surface of the carrier, and the carrier has a plurality of vias interconnecting the second lands and the pads.

51. The structure of claim 49 further comprising:

a plurality of solder balls, each solder ball bein located on a conductive pad on the carrier embedded in the substrate.

52. The structure of claim 49 wherein:

the carrier embedded in the substrate comprises an integrated circuit chip.

53. The electronic component of claim 49 where the embedded structure comprises at least one active device.

55. The electronic component of claim 49 where the embedded structure comprises at least one passive device.

58. The electronic component of claim 49 where the embedded structure comprises at least one passive device and at least one active device.

59. The electronic component of claim 49 where the substrate comprises a ceramic material.

54. The electronic component of claim 54 where the active device is a power transistor.

56. The electronic component of claim 56 where the passive device is a capacitor.

57. The electronic component of claim 56 where the passive device is a resistor.